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EM65571
130COM / 128SEG 65K Color STN LCD Driver
Product Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
August 2005
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM Windows is a trademark of Microsoft Corporation ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation
Copyright (c) 2005 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan, ROC
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai Corporation, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600
Contents
Contents
1 2 3 General Description .................................................................................................. 1 Feature ....................................................................................................................... 1 Applications............................................................................................................... 1 3.1 4 5 6 Pin Configuration ................................................................................................2 3.2 Pin Dimensions ...................................................................................................3 Functional Block Diagram...................................................................................... 12 Power Circuit Block Diagram ................................................................................. 13 Pin Description........................................................................................................ 14 6.1 6.2 6.3 6.4 6.5 7 Power Supply Pins............................................................................................14 LCD Power Supply Circuit Pins ........................................................................14 System Bus Pins...............................................................................................15 LCD Drive Circuit Signals .................................................................................16 Oscillating Circuit Pin ........................................................................................17
6.6 EEPROM Power Pin .........................................................................................17 Functional Description ........................................................................................... 17 7.1 MPU Interface ...................................................................................................17
7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 Reset Pin Description (RESB) ..........................................................................17 Selection of Interface Type................................................................................17 Parallel Input ....................................................................................................18 Read/Write Functions of the Registers and Display RAM ................................18 Serial Interface ..................................................................................................18 4-wire Serial Interface .......................................................................................18 3-Wire Type Serial Interface..............................................................................19
7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9
Data Write to Display RAM and Control Register .............................................20 Internal Register Read ......................................................................................20 16-Bit Data Access to Display RAM ..................................................................21 Fast Burst RAM Write Function ........................................................................21 Display Start Address Register .........................................................................22 Display RAM Addressing ..................................................................................22 Display RAM Access Using Windows Function ................................................25 Display RAM Data and LCD .............................................................................26
7.10 Segment Display Output Order/Reverse Set up ...............................................26 7.11 Relationship between Display RAM and Address.............................................27 7.12 Display Data Structure and Gradation Control..................................................35 7.13 Gradation LSB Control.....................................................................................41 7.14 Gradation Palette .............................................................................................42 7.15 Color Display (PWM+FRC) ..............................................................................47 7.16 Display Timing Circuit .......................................................................................49
Product Specification (V1.0) 08 04 2005 iii
Contents
7.17 Signal Generation to Display Line Counter and Display Data Latching Circuit ...49 7.18 Generation of the Alternated Signal and the Synchronous Signal ....................49 7.19 Display Data Latching Circuit............................................................................49 7.20 Output Timing of the LCD Driver.......................................................................50 7.21 LCD Driver Circuit .............................................................................................50 7.22 Oscillator Circuit................................................................................................51 7.23 Power Supply Circuit.........................................................................................51 7.24 Booster Circuit ..................................................................................................52 7.25 Electronic Volume .............................................................................................53 7.26 Voltage Regulator .............................................................................................53 7.27 Voltage Generator Circuit..................................................................................53 7.28 EEPROM Function............................................................................................56 7.29 Partial Display Function ....................................................................................59 7.30 Discharge Circuit...............................................................................................60 7.31 Initialization .......................................................................................................60 7.32 Precautionary Measures during Power ON and Power OFF ............................62
7.32.1 When Using an External Power Supply ............................................................62 7.32.2 When Using a Built-in Power Supply ................................................................62 7.32.3 Power Supply Rising Time ................................................................................62
7.33 Example of Register Setting .............................................................................63
7.33.1 Initialization........................................................................................................63 7.33.2 Display Data ......................................................................................................64 7.33.3 Power OFF ........................................................................................................64
8
Control Register ...................................................................................................... 65 8.1 8.2 Control Register ................................................................................................65 Control Register Functions ...............................................................................68
8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.2.13 8.2.14 8.2.15 8.2.16 8.2.17 X-address Register (AX) ...................................................................................69 Y-Address Register (AY) ...................................................................................69 Display Start Address Register (LA)..................................................................69 n-line Alternate Register (N)..............................................................................70 Display Control (1) Register ..............................................................................71 Display Control (2) Register ..............................................................................71 Increment Control Register Set.........................................................................73 Power Control Register .....................................................................................75 LCD Duty (DS) ..................................................................................................76 Booster Setup (VU) ...........................................................................................76 Bias Setting Register (B)...................................................................................77 Register Access Control....................................................................................77 Gradation Palette Register (PA0~PA7, PB0~PB7, PC0~PC7) .........................77 Display Start Common.......................................................................................87 Temperature Compensation Set .......................................................................87 Display Select Control .......................................................................................88 Data Bus Size Select.........................................................................................89
Product Specification (V1.0) 08.04.2005
iv *
Contents
8.2.18 8.2.19 8.2.20 8.2.21 8.2.22 8.2.23 8.2.24 8.2.25 8.2.26 8.2.27 8.2.28 8.2.29 8.2.30
Electronic Volume Register ...............................................................................89 Resistance Ratio of CR Oscillator.....................................................................91 Extended Power Control ...................................................................................91 Internal Register Read Address ........................................................................92 Internal Register Data Read..............................................................................92 Windows End X Address...................................................................................92 Windows End Y Address ...................................................................................93 Line Reverse Start Address..............................................................................93 Line Reverse End Address................................................................................93 Line Reverse Control.........................................................................................94 Regulator Multiple Ratio Control Register.........................................................95 EEPROM Mode Select Register .......................................................................96 Vop Calibration Offset Register.........................................................................96
9 10
Relationship between Setting and Common/Display RAM ................................. 97 Absolute Maximum Ratings ................................................................................... 98 10.1 Absolute Maximum Ratings ..............................................................................98 10.2 Recommended Operating Conditions...............................................................98 DC Characteristics .................................................................................................. 99 AC Characteristic .................................................................................................. 102 12.1 80-family MPU Write Timing ...........................................................................102 12.2 80-family MPU Read Timing ..........................................................................104 12.3 68-family MPU Write Timing ...........................................................................105 12.4 68-family MPU Read Timing ..........................................................................106 12.5 Serial Interface Timing Diagram.....................................................................108 12.6 Clock Input Timing .........................................................................................109 12.7 Reset Timing ..................................................................................................110 Application Circuit .................................................................................................110 13.1 Connections of the 80-family MPU ................................................................110 13.2 Connections of the 68-family MPU ................................................................ 111 13.3 Connection of the MPU with Serial Interface ................................................. 111 Tray Information .....................................................................................................112
11 12
13
14
Product Specification (V1.0) 08 04 2005
v
Contents
Specification Revision History
Version 0.1 0.2 0.3 0.4 0.5 Initial version Modified the bump size on page 6 Modified the VBA pin description on page 17 Modified the voltage generation circuit on page 57~58 Added V0 DC spec. on page 105 Modified the pin configurations on page 5~14 Modified the write timing "tWRLW8" values of the AC characteristics on page 110 and page 112 0.6 1.0 Modified the VBA application circuit Modified the DV Range 128 114 Removed the "Preliminary" water mark 2005/02/16 2005/08/04 2005/1/07 2005/1/24 Revision Description Date 2004/09/02 2004/11/04 2004/12/24
vi *
Product Specification (V1.0) 08.04.2005
EM65571
130COM/128SEG 65K Color STN LCD Driver
1
General Description
The EM65571 is one of the industry's most advanced wide-screen STN-LCD drivers for 65K-color displays. It has a built-in display RAM, a power supply circuit for LCD drive, an LCD controller circuit, and support for LCD cell tolerance compensation of VLCD by external pin selection. It also supports the EEPROM function for programming information to tune VLCD offset voltage to get the best contrast. Therefore, this contributes to a compact system design. In addition, its partial display function realizes low power consumption. *Partial display function: A function that utilizes only part of the screen, thus reducing power consumption.
2
Feature
65K-color display LCD output: Segment 128RGB (384 outputs); Common 128 outputs Display RAM capacity: 128x130x16=266240 bits Built-in display RAM and power supply circuit Partial display function Bus connection with 80-family/68-family MPU/ELAN MPU Logic power supply voltage: 2.2V to 3.3V LCD driving voltage: 5.0V to 20V Booster: 2 to 7 times Fast burst-RAM write function EEPROM function for tuning LCD operating voltage Vop Write system cycle: 200 ns Package:
Part Number EM65571AGH Package Gold bumped chip Description NA Package Information Page 5
Note: The EM65571 series has the following sub-codes, depending on their shapes. H: Bare chip (Aluminum pad without bump); GH: Gold bumped chip F: COF package; T: TAB (TCP) package
Example: EM65571AGH
EM65571: Elan number; A: Package Version; GH: Gold bumped chip
3
Applications
Mobile phone Small PDA
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
*1
EM65571
130COM/128SEG 65K Color STN LCD Driver
3.1 Pin Configuration
766 767 333 332
DDRAM
EM65571
799 1
the bottom left corner.
300 299
Note: With the Elan logo at the left corner (as shown in the figure) and DDRAM (black color) on the left side, Pin 1 is at
Figure 1. Pin Configuration
Mark U-Left D-Left
Coordinate (X, Y) -9836.85 , 376.85 -9836.85 , -372.55
Mark U-Right D-Right
Coordinate (X, Y) NA 9836.85 , -372.55
D-Left and D-Right:
U-Left and U-Right:
100m
40 20 100m 40
100m
40 20 40 100m
2*
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
3.2 Pin Dimensions
Item Chip size Pad No. X 1~28,272~299,333~766 Bump Size 300~332,767~799 30~270 29,271 Pad Pitch Die thickness 20580 30 70 42 48 45 (min.) 20+-1 mil (500+-25 m) 17+-3 m 15 Chip center Size Y 1720 70 30 59 70 m Unit
(excluding bumps)
Bump Height Minimum Bump Gap Coordinate Origin
Recommended Cog Ito Traces Resistor
Interface V0~V4 CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, CAP4+, CAP5+, CAP6+, Vout VDD, VEE VSSL, VSSH WRB, RDB, CSB,... D0~D7 RESB Max = 3K Max = 5~10K Max = 50 ITO Traces Resistances
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
*3
EM65571
130COM/128SEG 65K Color STN LCD Driver
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 4*
Pad Name NC1 COM109 COM111 COM113 COM115 COM117 COM119 COM121 COM123 COM125 COM127 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COMB NC2 VSSL VSSL VSSL VSSL VSSL VSSL VSSL VSSL VSSL VSSL VSSL VSSL TEST TEST TEST RESB RESB RESB CSB CSB CSB
Coordinate (X, Y) -9846.8 , -729.0 -9801.8 , -729.0 -9756.8 , -729.0 -9711.8 , -729.0 -9666.8 , -729.0 -9621.8 , -729.0 -9576.8 , -729.0 -9531.8 , -729.0 -9486.8 , -729.0 -9441.8 , -729.0 -9396.8 , -729.0 -9351.8 , -729.0 -9306.8 , -729.0 -9261.8 , -729.0 -9216.8 , -729.0 -9171.8 , -729.0 -9126.8 , -729.0 -9081.8 , -729.0 -9036.8 , -729.0 -8991.8 , -729.0 -8946.8 , -729.0 -8901.8 , -729.0 -8856.8 , -729.0 -8811.8 , -729.0 -8766.8 , -729.0 -8721.8 , -729.0 -8676.8 , -729.0 -8631.8 , -729.0 -8576.3 , -729.0 -8495.3 , -734.5 -8435.3 , -734.5 -8375.3 , -734.5 -8315.3 , -734.5 -8255.3 , -734.5 -8195.3 , -734.5 -8135.3 , -734.5 -8075.3 , -734.5 -8015.3 , -734.5 -7955.3 , -734.5 -7895.3 , -734.5 -7835.3 , -734.5 -7775.3 , -734.5 -7715.3 , -734.5 -7655.3 , -734.5 -7595.3 , -734.5 -7535.3 , -734.5 -7475.3 , -734.5 -7415.3 , -734.5 -7355.3 , -734.5 -7295.3 , -734.5
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Pad Name RS RS RS VSSL VSSL VSSL VDD VDD VDD P/S P/S P/S M86 M86 M86 VSSL VSSL VSSL VSSL WRB WRB WRB RDB RDB RDB VDD VDD VDD VPP VPP VPP NC14 D0 D0 D0 D1 D1 D1 D2 D2 D2 D3 D3 D3 D4 D4 D4 D5 D5 D5
Coordinate (X, Y) -7235.3 , -734.5 -7175.3 , -734.5 -7115.3 , -734.5 -7055.3 , -734.5 -6995.3 , -734.5 -6935.3 , -734.5 -6647.3 , -734.5 -6587.3 , -734.5 -6527.3 , -734.5 -6467.3 , -734.5 -6407.3 , -734.5 -6347.3 , -734.5 -6287.3 , -734.5 -6227.3 , -734.5 -6167.3 , -734.5 -6107.3 , -734.5 -6047.3 , -734.5 -5987.3 , -734.5 -5927.3 , -734.5 -5867.3 , -734.5 -5807.3 , -734.5 -5747.3 , -734.5 -5687.3 , -734.5 -5627.3 , -734.5 -5567.3 , -734.5 -5279.3 , -734.5 -5219.3 , -734.5 -5159.3 , -734.5 -4859.3 , -734.5 -4799.3 , -734.5 -4739.3 , -734.5 -4439.3 , -734.5 -4379.3 , -734.5 -4319.3 , -734.5 -4259.3 , -734.5 -4199.3 , -734.5 -4139.3 , -734.5 -4079.3 , -734.5 -4019.3 , -734.5 -3959.3 , -734.5 -3899.3 , -734.5 -3839.3 , -734.5 -3779.3 , -734.5 -3719.3 , -734.5 -3431.3 , -734.5 -3371.3 , -734.5 -3311.3 , -734.5 -3251.3 , -734.5 -3191.3 , -734.5 -3131.3 , -734.5
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Pad Name D6 D6 D6 D7 D7 D7 D8 D8 D8 D9 D9 D9 D10 D10 D10 D11 D11 D11 D12 D12 D12 D13 D13 D13 D14 D14 D14 D15 D15 D15 VSSL VSSL VSSL CK CK CK CKS CKS CKS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
Coordinate (X, Y) -3071.3 , -734.5 -3011.3 , -734.5 -2951.3 , -734.5 -2891.3 , -734.5 -2831.3 , -734.5 -2771.3 , -734.5 -2711.3 , -734.5 -2651.3 , -734.5 -2591.3 , -734.5 -2531.3 , -734.5 -2471.3 , -734.5 -2411.3 , -734.5 -2351.3 , -734.5 -2291.3 , -734.5 -2231.3 , -734.5 -2171.3 , -734.5 -2111.3 , -734.5 -2051.3 , -734.5 -1761.2 , -734.5 -1701.2 , -734.5 -1641.2 , -734.5 -1581.2 , -734.5 -1521.2 , -734.5 -1461.2 , -734.5 -1401.2 , -734.5 -1341.2 , -734.5 -1281.2 , -734.5 -1221.2 , -734.5 -1161.2 , -734.5 -1101.2 , -734.5 -1041.2 , -734.5 -981.2 , -734.5 -921.2 , -734.5 -861.2 , -734.5 -801.2 , -734.5 -741.2 , -734.5 -681.2 , -734.5 -621.2 , -734.5 -561.2 , -734.5 -273.2 , -734.5 -213.2 , -734.5 -153.2 , -734.5 -93.2 , -734.5 -33.2 , -734.5 26.8 , -734.5 86.8 , -734.5 146.8 , -734.5 206.8 , -734.5 266.8 , -734.5 326.8 , -734.5
Pin No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Pad Name VDD V0 V0 V0 V0 V0 V0 V1 V1 V1 V1 V1 V1 V2 V2 V2 V2 V2 V2 V3 V3 V3 V3 V3 V3 V4 V4 V4 V4 V4 V4 VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH NC3 VBA VBA VBA VBA VBA VBA VREF VREF VREF VREF
Coordinate (X, Y) 386.8 , -734.5 485.45 , -734.5 545.45 , -734.5 605.45 , -734.5 665.45 , -734.5 725.45 , -734.5 785.45 , -734.5 845.45 , -734.5 905.45 , -734.5 965.45 , -734.5 1025.45 , -734.5 1085.45 , -734.5 1145.45 , -734.5 1205.45 , -734.5 1265.45 , -734.5 1325.45 , -734.5 1385.45 , -734.5 1445.45 , -734.5 1505.45 , -734.5 1783.55 , -734.5 1843.55 , -734.5 1903.55 , -734.5 1963.55 , -734.5 2023.55 , -734.5 2083.55 , -734.5 2143.55 , -734.5 2203.55 , -734.5 2263.55 , -734.5 2323.55 , -734.5 2383.55 , -734.5 2443.55 , -734.5 2503.55 , -734.5 2563.55 , -734.5 2623.55 , -734.5 2683.55 , -734.5 2743.55 , -734.5 2803.55 , -734.5 2863.55 , -734.5 2923.55 , -734.5 2986.55 , -734.5 3267.9 , -734.5 3327.9 , -734.5 3387.9 , -734.5 3447.9 , -734.5 3507.9 , -734.5 3567.9 , -734.5 3627.9 , -734.5 3687.9 , -734.5 3747.9 , -734.5 3807.9 , -734.5
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
*5
EM65571
130COM/128SEG 65K Color STN LCD Driver
Pin No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Pad Name VREF VREF VEE VEE VEE VEE VEE VEE VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VOUT VOUT VOUT VOUT VOUT VOUT CAP1CAP1CAP1CAP1CAP1CAP1CAP1+ CAP1+ CAP1+ CAP1+ CAP1+ CAP1+ CAP2CAP2CAP2CAP2CAP2CAP2CAP2+ CAP2+ CAP2+ CAP2+ CAP2+ CAP2+ CAP3+ CAP3+ CAP3+ CAP3+
Coordinate (X, Y) 3867.9 , -734.5 3927.9 , -734.5 3987.9 , -734.5 4047.9 , -734.5 4107.9 , -734.5 4167.9 , -734.5 4227.9 , -734.5 4287.9 , -734.5 4347.9 , -734.5 4407.9 , -734.5 4467.9 , -734.5 4527.9 , -734.5 4587.9 , -734.5 4647.9 , -734.5 4707.9 , -734.5 4767.9 , -734.5 4827.9 , -734.5 4887.9 , -734.5 4947.9 , -734.5 5007.9 , -734.5 5067.9 , -734.5 5127.9 , -734.5 5187.9 , -734.5 5247.9 , -734.5 5307.9 , -734.5 5367.9 , -734.5 5427.9 , -734.5 5487.9 , -734.5 5791.9 , -734.5 5851.9 , -734.5 5911.9 , -734.5 5971.9 , -734.5 6031.9 , -734.5 6091.9 , -734.5 6151.9 , -734.5 6211.9 , -734.5 6271.9 , -734.5 6331.9 , -734.5 6391.9 , -734.5 6451.9 , -734.5 6511.9 , -734.5 6571.9 , -734.5 6631.9 , -734.5 6691.9 , -734.5 6751.9 , -734.5 6811.9 , -734.5 6871.9 , -734.5 6931.9 , -734.5 6991.9 , -734.5 7051.9 , -734.5
Pin No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
Pad Name CAP3+ CAP3+ CAP4+ CAP4+ CAP4+ CAP4+ CAP4+ CAP4+ CAP5+ CAP5+ CAP5+ CAP5+ CAP5+ CAP5+ CAP6+ CAP6+ CAP6+ CAP6+ CAP6+ CAP6+ NC4 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM126 COM124 COM122 COM120 COM118 COM116 COM114 COM112 COM110 COM108 COM106 NC5 NC6
Coordinate (X, Y) 7111.9 , -734.5 7171.9 , -734.5 7231.9 , -734.5 7291.9 , -734.5 7351.9 , -734.5 7411.9 , -734.5 7471.9 , -734.5 7531.9 , -734.5 7835.3 , -734.5 7895.3 , -734.5 7955.3 , -734.5 8015.3 , -734.5 8075.3 , -734.5 8135.3 , -734.5 8195.3 , -734.5 8255.3 , -734.5 8315.3 , -734.5 8375.3 , -734.5 8435.3 , -734.5 8495.3 , -734.5 8576.3 , -729.0 8631.8 , -729.0 8676.8 , -729.0 8721.8 , -729.0 8766.8 , -729.0 8811.8 , -729.0 8856.8 , -729.0 8901.8 , -729.0 8946.8 , -729.0 8991.8 , -729.0 9036.8 , -729.0 9081.8 , -729.0 9126.8 , -729.0 9171.8 , -729.0 9216.8 , -729.0 9261.8 , -729.0 9306.8 , -729.0 9351.8 , -729.0 9396.8 , -729.0 9441.8 , -729.0 9486.8 , -729.0 9531.8 , -729.0 9576.8 , -729.0 9621.8 , -729.0 9666.8 , -729.0 9711.8 , -729.0 9756.8 , -729.0 9801.8 , -729.0 9846.8 , -729.0 10159.0 , -720.0
6*
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
Pin No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350
Pad Name COM104 COM102 COM100 COM98 COM96 COM94 COM92 COM90 COM88 COM86 COM84 COM82 COM80 COM78 COM76 COM74 COM72 COM70 COM68 COM66 COM64 COM62 COM60 COM58 COM56 COM54 COM52 COM50 COM48 COM46 COM44 NC7 NC8 COM42 COM40 COM38 COM36 COM34 COM32 COM30 COM28 COM26 COM24 COM22 COM20 COM18 COM16 COM14 COM12 COM10
Coordinate (X, Y) 10159.0 , -675.0 10159.0 , -630.0 10159.0 , -585.0 10159.0 , -540.0 10159.0 , -495.0 10159.0 , -450.0 10159.0 , -405.0 10159.0 , -360.0 10159.0 , -315.0 10159.0 , -270.0 10159.0 , -225.0 10159.0 , -180.0 10159.0 , -135.0 10159.0 , -90.0 10159.0 , -45.0 10159. 0, 0.0 10159.0 , 45.0 10159.0 , 90.0 10159.0 , 135.0 10159.0 , 180.0 10159.0 , 225.0 10159.0 , 270.0 10159.0 , 315.0 10159.0 , 360.0 10159.0 , 405.0 10159.0 , 450.0 10159.0 , 495.0 10159.0 , 540.0 10159.0 , 585.0 10159.0 , 630.0 10159.0 , 675.0 10159.0 , 720.0 9846.8 , 729.0 9801.8 , 729.0 9756.8 , 729.0 9711.8 , 729.0 9666.8 , 729.0 9621.8 , 729.0 9576.8 , 729.0 9531.8 , 729.0 9486.8 , 729.0 9441.8 , 729.0 9396.8 , 729.0 9351.8 , 729.0 9306.8 , 729.0 9261.8 , 729.0 9216.8 , 729.0 9171.8 , 729.0 9126.8 , 729.0 9081.8 , 729.0
Pin No. 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400
Pad Name COM8 COM6 COM4 COM2 COM0 COMA NC9 SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 SEGA2 SEGB2 SEGC2 SEGA3 SEGB3 SEGC3 SEGA4 SEGB4 SEGC4 SEGA5 SEGB5 SEGC5 SEGA6 SEGB6 SEGC6 SEGA7 SEGB7 SEGC7 SEGA8 SEGB8 SEGC8 SEGA9 SEGB9 SEGC9 SEGA10 SEGB10 SEGC10 SEGA11 SEGB11 SEGC11 SEGA12 SEGB12 SEGC12 SEGA13 SEGB13 SEGC13 SEGA14
Coordinate (X, Y) 9036.8 , 729.0 8991.8 , 729.0 8946.8 , 729.0 8901.8 , 729.0 8856.8 , 729.0 8811.8 , 729.0 8766.8 , 729.0 8721.8 , 729.0 8676.8 , 729.0 8631.8 , 729.0 8586.8 , 729.0 8541.8 , 729.0 8496.8 , 729.0 8451.8 , 729.0 8406.8 , 729.0 8361.8 , 729.0 8316.8 , 729.0 8271.8 , 729.0 8226.8 , 729.0 8181.8 , 729.0 8136.8 , 729.0 8091.8 , 729.0 8046.8 , 729.0 8001.8 , 729.0 7956.8 , 729.0 7911.8 , 729.0 7866.8 , 729.0 7821.8 , 729.0 7776.8 , 729.0 7731.8 , 729.0 7686.8 , 729.0 7641.8 , 729.0 7596.8 , 729.0 7551.8 , 729.0 7506.8 , 729.0 7461.8 , 729.0 7416.8 , 729.0 7371.8 , 729.0 7326.8 , 729.0 7281.8 , 729.0 7236.8 , 729.0 7191.8 , 729.0 7146.8 , 729.0 7101.8 , 729.0 7056.8 , 729.0 7011.8 , 729.0 6966.8 , 729.0 6921.8 , 729.0 6876.8 , 729.0 6831.8 , 729.0
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
*7
EM65571
130COM/128SEG 65K Color STN LCD Driver
Pin No. 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450
Pad Name SEGB14 SEGC14 SEGA15 SEGB15 SEGC15 SEGA16 SEGB16 SEGC16 SEGA17 SEGB17 SEGC17 SEGA18 SEGB18 SEGC18 SEGA19 SEGB19 SEGC19 SEGA20 SEGB20 SEGC20 SEGA21 SEGB21 SEGC21 SEGA22 SEGB22 SEGC22 SEGA23 SEGB23 SEGC23 SEGA24 SEGB24 SEGC24 SEGA25 SEGB25 SEGC25 SEGA26 SEGB26 SEGC26 SEGA27 SEGB27 SEGC27 SEGA28 SEGB28 SEGC28 SEGA29 SEGB29 SEGC29 SEGA30 SEGB30 SEGC30
Coordinate (X, Y) 6786.8 , 729.0 6741.8 , 729.0 6696.8 , 729.0 6651.8 , 729.0 6606.8 , 729.0 6561.8 , 729.0 6516.8 , 729.0 6471.8 , 729.0 6426.8 , 729.0 6381.8 , 729.0 6336.8 , 729.0 6291.8 , 729.0 6246.8 , 729.0 6201.8 , 729.0 6156.8 , 729.0 6111.8 , 729.0 6066.8 , 729.0 6021.8 , 729.0 5976.8 , 729.0 5931.8 , 729.0 5886.8 , 729.0 5841.8 , 729.0 5796.8 , 729.0 5751.8 , 729.0 5706.8 , 729.0 5661.8 , 729.0 5616.8 , 729.0 5571.8 , 729.0 5526.8 , 729.0 5481.8 , 729.0 5436.8 , 729.0 5391.8 , 729.0 5346.8 , 729.0 5301.8 , 729.0 5256.8 , 729.0 5211.8 , 729.0 5166.8 , 729.0 5121.8 , 729.0 5076.8 , 729.0 5031.8 , 729.0 4986.8 , 729.0 4941.8 , 729.0 4896.8 , 729.0 4851.8 , 729.0 4806.8 , 729.0 4761.8 , 729.0 4716.8 , 729.0 4671.8 , 729.0 4626.8 , 729.0 4581.8 , 729.0
Pin No. 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500
Pad Name SEGA31 SEGB31 SEGC31 SEGA32 SEGB32 SEGC32 SEGA33 SEGB33 SEGC33 SEGA34 SEGB34 SEGC34 SEGA35 SEGB35 SEGC35 SEGA36 SEGB36 SEGC36 SEGA37 SEGB37 SEGC37 SEGA38 SEGB38 SEGC38 SEGA39 SEGB39 SEGC39 SEGA40 SEGB40 SEGC40 SEGA41 SEGB41 SEGC41 SEGA42 SEGB42 SEGC42 SEGA43 SEGB43 SEGC43 SEGA44 SEGB44 SEGC44 SEGA45 SEGB45 SEGC45 SEGA46 SEGB46 SEGC46 SEGA47 SEGB47
Coordinate (X, Y) 4536.8 , 729.0 4491.8 , 729.0 4446.8 , 729.0 4401.8 , 729.0 4356.8 , 729.0 4311.8 , 729.0 4266.8 , 729.0 4221.8 , 729.0 4176.8 , 729.0 4131.8 , 729.0 4086.8 , 729.0 4041.8 , 729.0 3996.8 , 729.0 3951.8 , 729.0 3906.8 , 729.0 3861.8 , 729.0 3816.8 , 729.0 3771.8 , 729.0 3726.8 , 729.0 3681.8 , 729.0 3636.8 , 729.0 3591.8 , 729.0 3546.8 , 729.0 3501.8 , 729.0 3456.8 , 729.0 3411.8 , 729.0 3366.8 , 729.0 3321.8 , 729.0 3276.8 , 729.0 3231.8 , 729.0 3186.8 , 729.0 3141.8 , 729.0 3096.8 , 729.0 3051.8 , 729.0 3006.8 , 729.0 2961.8 , 729.0 2916.8 , 729.0 2871.8 , 729.0 2826.8 , 729.0 2781.8 , 729.0 2736.8 , 729.0 2691.8 , 729.0 2646.8 , 729.0 2601.8 , 729.0 2556.8 , 729.0 2511.8 , 729.0 2466.8 , 729.0 2421.8 , 729.0 2376.8 , 729.0 2331.8 , 729.0
8*
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
Pin No. 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550
Pad Name SEGC47 SEGA48 SEGB48 SEGC48 SEGA49 SEGB49 SEGC49 SEGA50 SEGB50 SEGC50 SEGA51 SEGB51 SEGC51 SEGA52 SEGB52 SEGC52 SEGA53 SEGB53 SEGC53 SEGA54 SEGB54 SEGC54 SEGA55 SEGB55 SEGC55 SEGA56 SEGB56 SEGC56 SEGA57 SEGB57 SEGC57 SEGA58 SEGB58 SEGC58 SEGA59 SEGB59 SEGC59 SEGA60 SEGB60 SEGC60 SEGA61 SEGB61 SEGC61 SEGA62 SEGB62 SEGC62 SEGA63 SEGB63 SEGC63 SEGA64
Coordinate (X, Y) 2286.8 , 729.0 2241.8 , 729.0 2196.8 , 729.0 2151.8 , 729.0 2106.8 , 729.0 2061.8 , 729.0 2016.8 , 729.0 1971.8 , 729.0 1926.8 , 729.0 1881.8 , 729.0 1836.8 , 729.0 1791.8 , 729.0 1746.8 , 729.0 1701.8 , 729.0 1656.8 , 729.0 1611.8 , 729.0 1566.8 , 729.0 1521.8 , 729.0 1476.8 , 729.0 1431.8 , 729.0 1386.8 , 729.0 1341.8 , 729.0 1296.8 , 729.0 1251.8 , 729.0 1206.8 , 729.0 1161.8 , 729.0 1116.8 , 729.0 1071.8 , 729.0 1026.8 , 729.0 981.8 , 729.0 936.8 , 729.0 891.8 , 729.0 846.8 , 729.0 801.8 , 729.0 756.8 , 729.0 711.8 , 729.0 666.8 , 729.0 621.8 , 729.0 576.8 , 729.0 531.8 , 729.0 486.8 , 729.0 441.8 , 729.0 396.8 , 729.0 351.8 , 729.0 306.8 , 729.0 261.8 , 729.0 216.8 , 729.0 171.8 , 729.0 126.8 , 729.0 -126.8 , 729.0
Pin No. 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600
Pad Name SEGB64 SEGC64 SEGA65 SEGB65 SEGC65 SEGA66 SEGB66 SEGC66 SEGA67 SEGB67 SEGC67 SEGA68 SEGB68 SEGC68 SEGA69 SEGB69 SEGC69 SEGA70 SEGB70 SEGC70 SEGA71 SEGB71 SEGC71 SEGA72 SEGB72 SEGC72 SEGA73 SEGB73 SEGC73 SEGA74 SEGB74 SEGC74 SEGA75 SEGB75 SEGC75 SEGA76 SEGB76 SEGC76 SEGA77 SEGB77 SEGC77 SEGA78 SEGB78 SEGC78 SEGA79 SEGB79 SEGC79 SEGA80 SEGB80 SEGC80
Coordinate (X, Y) -171.8 , 729.0 -216.8 , 729.0 -261.8 , 729.0 -306.8 , 729.0 -351.8 , 729.0 -396.8 , 729.0 -441.8 , 729.0 -486.8 , 729.0 -531.8 , 729.0 -576.8 , 729.0 -621.8 , 729.0 -666.8 , 729.0 -711.8 , 729.0 -756.8 , 729.0 -801.8 , 729.0 -846.8 , 729.0 -891.8 , 729.0 -936.8 , 729.0 -981.8 , 729.0 -1026.8 , 729.0 -1071.8 , 729.0 -1116.8 , 729.0 -1161.8 , 729.0 -1206.8 , 729.0 -1251.8 , 729.0 -1296.8 , 729.0 -1341.8 , 729.0 -1386.8 , 729.0 -1431.8 , 729.0 -1476.8 , 729.0 -1521.8 , 729.0 -1566.8 , 729.0 -1611.8 , 729.0 -1656.8 , 729.0 -1701.8 , 729.0 -1746.8 , 729.0 -1791.8 , 729.0 -1836.8 , 729.0 -1881.8 , 729.0 -1926.8 , 729.0 -1971.8 , 729.0 -2016.8 , 729.0 -2061.8 , 729.0 -2106.8 , 729.0 -2151.8 , 729.0 -2196.8 , 729.0 -2241.8 , 729.0 -2286.8 , 729.0 -2331.8 , 729.0 -2376.8 , 729.0
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
*9
EM65571
130COM/128SEG 65K Color STN LCD Driver
Pin No. 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650
Pad Name SEGA81 SEGB81 SEGC81 SEGA82 SEGB82 SEGC82 SEGA83 SEGB83 SEGC83 SEGA84 SEGB84 SEGC84 SEGA85 SEGB85 SEGC85 SEGA86 SEGB86 SEGC86 SEGA87 SEGB87 SEGC87 SEGA88 SEGB88 SEGC88 SEGA89 SEGB89 SEGC89 SEGA90 SEGB90 SEGC90 SEGA91 SEGB91 SEGC91 SEGA92 SEGB92 SEGC92 SEGA93 SEGB93 SEGC93 SEGA94 SEGB94 SEGC94 SEGA95 SEGB95 SEGC95 SEGA96 SEGB96 SEGC96 SEGA97 SEGB97
Coordinate (X, Y) -2421.8 , 729.0 -2466.8 , 729.0 -2511.8 , 729.0 -2556.8 , 729.0 -2601.8 , 729.0 -2646.8 , 729.0 -2691.8 , 729.0 -2736.8 , 729.0 -2781.8 , 729.0 -2826.8 , 729.0 -2871.8 , 729.0 -2916.8 , 729.0 -2961.8 , 729.0 -3006.8 , 729.0 -3051.8 , 729.0 -3096.8 , 729.0 -3141.8 , 729.0 -3186.8 , 729.0 -3231.8 , 729.0 -3276.8 , 729.0 -3321.8 , 729.0 -3366.8 , 729.0 -3411.8 , 729.0 -3456.8 , 729.0 -3501.8 , 729.0 -3546.8 , 729.0 -3591.8 , 729.0 -3636.8 , 729.0 -3681.8 , 729.0 -3726.8 , 729.0 -3771.8 , 729.0 -3816.8 , 729.0 -3861.8 , 729.0 -3906.8 , 729.0 -3951.8 , 729.0 -3996.8 , 729.0 -4041.8 , 729.0 -4086.8 , 729.0 -4131.8 , 729.0 -4176.8 , 729.0 -4221.8 , 729.0 -4266.8 , 729.0 -4311.8 , 729.0 -4356.8 , 729.0 -4401.8 , 729.0 -4446.8 , 729.0 -4491.8 , 729.0 -4536.8 , 729.0 -4581.8 , 729.0 -4626.8 , 729.0
Pin No. 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700
Pad Name SEGC97 SEGA98 SEGB98 SEGC98 SEGA99 SEGB99 SEGC99 SEGA100 SEGB100 SEGC100 SEGA101 SEGB101 SEGC101 SEGA102 SEGB102 SEGC102 SEGA103 SEGB103 SEGC103 SEGA104 SEGB104 SEGC104 SEGA105 SEGB105 SEGC105 SEGA106 SEGB106 SEGC106 SEGA107 SEGB107 SEGC107 SEGA108 SEGB108 SEGC108 SEGA109 SEGB109 SEGC109 SEGA110 SEGB110 SEGC110 SEGA111 SEGB111 SEGC111 SEGA112 SEGB112 SEGC112 SEGA113 SEGB113 SEGC113 SEGA114
Coordinate (X, Y) -4671.8 , 729.0 -4716.8 , 729.0 -4761.8 , 729.0 -4806.8 , 729.0 -4851.8 , 729.0 -4896.8 , 729.0 -4941.8 , 729.0 -4986.8 , 729.0 -5031.8 , 729.0 -5076.8 , 729.0 -5121.8 , 729.0 -5166.8 , 729.0 -5211.8 , 729.0 -5256.8 , 729.0 -5301.8 , 729.0 -5346.8 , 729.0 -5391.8 , 729.0 -5436.8 , 729.0 -5481.8 , 729.0 -5526.8 , 729.0 -5571.8 , 729.0 -5616.8 , 729.0 -5661.8 , 729.0 -5706.8 , 729.0 -5751.8 , 729.0 -5796.8 , 729.0 -5841.8 , 729.0 -5886.8 , 729.0 -5931.8 , 729.0 -5976.8 , 729.0 -6021.8 , 729.0 -6066.8 , 729.0 -6111.8 , 729.0 -6156.8 , 729.0 -6201.8 , 729.0 -6246.8 , 729.0 -6291.8 , 729.0 -6336.8 , 729.0 -6381.8 , 729.0 -6426.8 , 729.0 -6471.8 , 729.0 -6516.8 , 729.0 -6561.8 , 729.0 -6606.8 , 729.0 -6651.8 , 729.0 -6696.8 , 729.0 -6741.8 , 729.0 -6786.8 , 729.0 -6831.8 , 729.0 -6876.8 , 729.0
10 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
Pin No. 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750
Pad Name SEGB114 SEGC114 SEGA115 SEGB115 SEGC115 SEGA116 SEGB116 SEGC116 SEGA117 SEGB117 SEGC117 SEGA118 SEGB118 SEGC118 SEGA119 SEGB119 SEGC119 SEGA120 SEGB120 SEGC120 SEGA121 SEGB121 SEGC121 SEGA122 SEGB122 SEGC122 SEGA123 SEGB123 SEGC123 SEGA124 SEGB124 SEGC124 SEGA125 SEGB125 SEGC125 SEGA126 SEGB126 SEGC126 SEGA127 SEGB127 SEGC127 NC10 COM1 COM3 COM5 COM7 COM9 COM11 COM13 COM15
Coordinate (X, Y) -6921.8 , 729.0 -6966.8 , 729.0 -7011.8 , 729.0 -7056.8 , 729.0 -7101.8 , 729.0 -7146.8 , 729.0 -7191.8 , 729.0 -7236.8 , 729.0 -7281.8 , 729.0 -7326.8 , 729.0 -7371.8 , 729.0 -7416.8 , 729.0 -7461.8 , 729.0 -7506.8 , 729.0 -7551.8 , 729.0 -7596.8 , 729.0 -7641.8 , 729.0 -7686.8 , 729.0 -7731.8 , 729.0 -7776.8 , 729.0 -7821.8 , 729.0 -7866.8 , 729.0 -7911.8 , 729.0 -7956.8 , 729.0 -8001.8 , 729.0 -8046.8 , 729.0 -8091.8 , 729.0 -8136.8 , 729.0 -8181.8 , 729.0 -8226.8 , 729.0 -8271.8 , 729.0 -8316.8 , 729.0 -8361.8 , 729.0 -8406.8 , 729.0 -8451.8 , 729.0 -8496.8 , 729.0 -8541.8 , 729.0 -8586.8 , 729.0 -8631.8 , 729.0 -8676.8 , 729.0 -8721.8 , 729.0 -8766.8 , 729.0 -8811.8 , 729.0 -8856.8 , 729.0 -8901.8 , 729.0 -8946.8 , 729.0 -8991.8 , 729.0 -9036.8 , 729.0 -9081.8 , 729.0 -9126.8 , 729.0
Pin No. 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799
Pad Name COM17 COM19 COM21 COM23 COM25 COM27 COM29 COM31 COM33 COM35 COM37 COM39 COM41 COM43 COM45 NC11 NC12 COM47 COM49 COM51 COM53 COM55 COM57 COM59 COM61 COM63 COM65 COM67 COM69 COM71 COM73 COM75 COM77 COM79 COM81 COM83 COM85 COM87 COM89 COM91 COM93 COM95 COM97 COM99 COM101 COM103 COM105 COM107 NC13
Coordinate (X, Y) -9171.8 , 729.0 -9216.8 , 729.0 -9261.8 , 729.0 -9306.8 , 729.0 -9351.8 , 729.0 -9396.8 , 729.0 -9441.8 , 729.0 -9486.8 , 729.0 -9531.8 , 729.0 -9576.8 , 729.0 -9621.8 , 729.0 -9666.8 , 729.0 -9711.8 , 729.0 -9756.8 , 729.0 -9801.8 , 729.0 -9846.8 , 729.0 -10159.0 , 720.0 -10159.0 , 675.0 -10159.0 , 630.0 -10159.0 , 585.0 -10159.0 , 540.0 -10159.0 , 495.0 -10159.0 , 450.0 -10159.0 , 405.0 -10159.0 , 360.0 -10159.0 , 315.0 -10159.0 , 270.0 -10159.0 , 225.0 -10159.0 , 180.0 -10159.0 , 135.0 -10159.0 , 90.0 -10159.0 , 45.0 -10159.0 , 0.0 -10159.0 , -45.0 -10159.0 , -90.0 -10159.0 , - 135.0 -10159.0 , -180.0 -10159.0 , -225.0 -10159.0 , -270.0 -10159.0 , -315.0 -10159.0 , -360.0 -10159.0 , -405.0 -10159.0 , -450.0 -10159.0 , -495.0 -10159.0 , -540.0 -10159.0 , -585.0 -10159.0 , -630.0 -10159.0 , -675.0 -10159.0 , -720.0
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 11
EM65571
130COM/128SEG 65K Color STN LCD Driver
4
Functional Block Diagram
SEGC127 SEGB127 SEGA127 COM127 SEGC0 SEGB0 SEGA0 COMB COMA COM0
VDD V0 V1 V2 V3 V4 VSS (VSSH, VSSL)
----
--------Segment Driver Gradation Selection Circuit Data Latch
Common Driver Shift Register
CAP1CAP1+ CAP2CAP2+ CAP3+ CAP4+ CAP5+ CAP6+ VOUT VEE VREF VBA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4/SPOL D3/SMODE D2 D1/SDA D0/SCL
Line Address Decoder
Display Line Register
Display Line Counter
Y Address Decoder
Y Address Register
Y Address Counter
Display RAM (DDRAM) 128 X 128 X (5+6+5) bits
Voltage Converter
Booster Circuit Input/Output Buffer
Pixel Display RAM (PGRAM) 128 X 2 X (5+6+5) bits X Address Decoder
RAM Interface X Address Counter
X Address Register
Alternation Circuit
Bus Holder
Instruction Decoder
Register Read
MPU Interface
OSC
Display Timing Gen.
CSB RS RDB WRB P/S M86 RESB TEST (E) (R/WB)
CK CKS
Figure 2. System Block Diagram
12 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
5
Power Circuit Block Diagram
VREF Temperature Compensation Vop Calibration Offset Register
Electronic Volume Register
VBA
VBA AMP
+ -
V0
V1
V2
Regulator Multiple Ratio Control Register
Bias Register
V3
Booster Step Set Register
V4
Impedance Converter
VEE
Booster Circuit
VOUT
CAP2+
CAP3+
CAP1-
Figure 3. Power Circuit Block Diagram
CAP1+
CAP4+
CAP5+ CAP6+
CAP2-
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 13
EM65571
130COM/128SEG 65K Color STN LCD Driver
6
Pin Description
6.1 Power Supply Pins
Symbol VDD VSSL VSSH V0 V1 V2 V3 V4 - I/O - - - Description Power supply pin for logic circuit, +2.2V to 3.3V Ground pin for logic circuit, connected to 0V Ground pin for high voltage circuit, connected to 0V Bias power supply pin for LCD drive voltage When using an external power supply, convert the impedance by using resistance-division of the LCD drive power supply or operation amplifier before adding voltage to the pins. These voltages should have the following relationship: VSS6.2 LCD Power Supply Circuit Pins
Symbol CAP1+ CAP1CAP2+ CAP2CAP3+ CAP4+ CAP5+ CAP6+ VEE VOUT VBA VREF I/O O O O O O O O O - O O O Description Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP1- and CAP1+. Connecting pin for the built in booster's capacitor - side. The capacitor is connected between CAP1- and CAP1+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP2- and CAP2+. Connecting pin for the built in booster's capacitor - side. The capacitor is connected between CAP2- and CAP2+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP1- and CAP3+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP2- and CAP4+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP1- and CAP5+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP2- and CAP6+. Voltage supply pin for the booster circuit. Usually the same voltage level as VDD. In the case of TCP, draw it at a separate terminal. Output pin of boosted voltage in the built-in booster. The capacitor must be connected between this pin and the VSS. Output pin for regulator voltage of VBA AMP. Output pin for temperature compensation output voltage.
14 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
6.3 System Bus Pins
Symbol RESB I/O I Reset input pin. When RESB is "L", initialization is executed. Data bus / Signal interface related pins. When parallel interface is selected (P/S = "H"), the D7-D0 are 8-bit bi-directional data busses, connected to the MPU data bus. *When serial interface is selected (P/S = "L"), D0 and D1 (SCL, SDA) are used as serial interface pins. SCL: Input pin for data transfer clock I/O SDA: Serial data input pin SMODE: Serial transfer mode select pin SPOL: RS pole select pin when 3-wires serial interface is selected. SDA data is latched at the rising edge of SCL. Internal serial/parallel conversion into 8-bit data occurs at the rising edge of the 8th clock of SCL. After completing data transfer, or when making no access, be sure to set SCL to "L". D8-D15 I/O 8-bit bi-directional bus. Connected to MPU data bus. Used as a data bus for the upper 8 pins in the 16-bit access mode. Chip Select input pin. CSB I CSB = "L": accepts access from the MPU CSB = "H": denies access from the MPU RAM/Register select input pin. RS I RS = "0": D7-D0 are display RAM data RS = "1": D7-D0 are control register data Read/Write control pin. Select 80-family MPU type (M86 = "L") RDB (E) The RDB is a data read signal. When RDB is "L", D7-D0 are in an output status. Select 68-family MPU type (M86 = "H") R/WB = "H": When E is "H", D7-D0 are in an output status. R/WB = "L": The data on D7-D0 are latched at the falling edge of the E signal. Read/Write control pin. Select 80-family MPU type (M86 = "L") WRB (R/WB) I The WRB is a data write signal. The data on D7-D0 are latched at the rising edge of the WRB signal. Select 68-family MPU type (M86 = "H") Read/Write control input pin. R/W = "H": Read R/W = "L": Write MPU interface type selecting input pin. M86 I M86 = "H": 68-family interface M86 = "L": 80-family interface Fixed at either "H" or "L" Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
Description
D0/SCL D1/SDA D2 D3/SMODE D4.SPOL D5-D7
I
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EM65571
130COM/128SEG 65K Color STN LCD Driver
Symbol TEST
I/O I For testing. Fix to "L"
Description
Parallel/Serial interface select pin. P/S P/S I H L Chip select CSB CSB Data Identification RS RS Data Read/Write Serial Clock SCL
D0-D7 RDB, WRB SDA Write only
P/S = "H": For parallel interface P/S = "L": For serial interface. Fix D15-D5 pins to Hi-Z, and fix RDB and WRB pins to either "H" or "L"
6.4 LCD Drive Circuit Signals
Symbol I/O Description Segment output pins for the LCD driver. Basing on the Display RAM data, non-lighted at "0", lighted at "1" (Normal Mode), non-lighted at "1", lighted at "0" (Reverse Mode) and by a combination of M signal and display data, one signal level among V0, V2, V3 and VSS signal level is selected. SEGA0-A127 SEGB0-B127 SEGC0-C127 O (For Monochrome Display)
M Signal (internal) Display RAM Data Normal Mode Reverse Mode V2 V0 V0 V2 V3 VSS VSS V3
COM0COM127
O
Common output pins for the LCD drivers. By a combination of the scanning data and M signal, one signal level among V0, V1, V4 and VSS signal level is selected. Data M Output Level H H VSS L H V1 H L V0 L L V4 Common output pin for LCD drive exclusively for icons. Common output pin for LCD drive exclusively for icons.
COMA COMB
O O
16 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
6.5 Oscillating Circuit Pin
Symbol I/O Description Display timing clock source select input pin. CKS I CKS = "H": Use external clock from the CK pin. CKS = "L": Use internal oscillator clock. In the case of TCP, draw it as a separate terminal. CK I External clock input pin for display timing (CKS=1). When using internal oscillator clock, connect CK to VSS (CKS=0).
6.6 EEPROM Power Pin
Symbol VPP I/O I Description External power supply pin for EEPROM programming or erasing. When using external power for EEPROM programming or erasing, the power supply is 16V~18V.
7
Functional Description
7.1 MPU Interface
7.1.1 Reset Pin Description (RESB)
Hold the RESB low for at least 10s, then the EM65571 accepts this reset command.
RESB
T > 10
7.1.2 Selection of Interface Type
The EM65571 transfers data through an 8-bit parallel I/O (D7-D0), 16-bit parallel I/O (D15-D0) or serial data input (SDA, SCL). The parallel interface or serial interface can be selected by the state of the P/S pin. When selecting serial interface, data reading cannot be performed, only data writing can operate.
P/S H L I/F Type Parallel Serial CSB CSB CSB RS RS RS RDB RDB WRB WRB M86 M86 SDA SDA SCL SCL Data D7~D0 (D15~D0) -
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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EM65571
130COM/128SEG 65K Color STN LCD Driver
7.1.3 Parallel Input
When parallel interface is selected with the P/S pin, the EM65571 allows data to be transferred in parallel to an 8-bit/16-bit MPU through the data bus. For the 8-bit/16-bit MPU, either the 80-family MPU interface or the 68-family MPU interface can be selected with the M86 pin.
M86 H L MPU Type 68-family MPU 80-family MPU CSB CSB CSB RS RS RS RDB E RDB WRB R/WB WRB Data D7~D0 (D15~D0) D0~D7 (D15~D0)
7.1.4 Read/Write Functions of the Registers and Display RAM
The EM65571 has four read/write functions during parallel interface mode. Each read/write function is selected by combinations of RS, RDB and WRB signals.
RS 1 1 0 0 68-family R/WB 1 0 1 0 RDB 0 1 0 1 80-family WRB 1 0 1 0 Read internal Register Write internal Register Read display data Write display data Function
7.1.5 Serial Interface
The EM65571 has two types of serial interface. One is a 3-wire type serial interface; the other one is a 4-wire type serial interface. The choice whether 3-wire or 4-wire is determined by the SMODE pin. SMODE = "L": 4-wires serial interface SMODE = "H": 3-wires serial interface
7.1.6 4-wire Serial Interface
When chip select is active (CSB = "L"), 4-wire type serial interface can work through the SDA and SCL input pins. When chip select is inactive (CSB = "H"), the internal shift register and counter are reset to the initial condition. Serial data SDA is input sequentially in the order from D7 to D0 at the rising edge of the serial clock (SCL) and is converted into 8-bit parallel data (by serial to parallel conversion) at the rising edge of the 8th serial clock, processed in accordance with the data. The identification whether serial data input (SDA), display data or control register data is determined by input to the RS pin. RS = "L" : display RAM data RS = "H" : control register data
18 * Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
After completion of an 8-bit data transfer, or when making no access, be sure to set the serial clock input (SCL) to "L". Care of the SDA and SCL signals against external noise should be taken into consideration during board wiring. To prevent transfer error due to external noise, release the chip select (CSB = "H") after every completion of an 8-bit data transfer.
CSB RS SDA SCL
1 2 3 4 5 6 7 8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4. 4-wire Type Serial Interface
7.1.7 3-Wire Type Serial Interface
When chip select is active (CSB = "L"), 3-wire type serial interface can work through the SDA and SCL input pins. When chip select is inactive (CSB = "H"), the internal shift register and counter are reset to the initial condition. Serial data SDA is input sequentially in the order from RS, D7 to D0 at the rising edge of the serial clock (SCL) and is converted into 9-bit parallel data (by serial to parallel conversion) at the rising edge of the 9th serial clock. The identification whether serial data input (SDA), display data or control register data is determined by the first serial input data (RS) and SPOL pin as follows.
SPOL = "0" RS 0 1 Display RAM/Register Display RAM Data Control Register Data RS 0 1 SPOL = "1" Display RAM/Register Control Register Data Display RAM Data
After completion of a 9-bit data transfer, or when making no access, be sure to set the serial clock input (SCL) to "L". Care of the SDA and SCL signals against external noise should be taken into consideration during board wiring. To prevent transfer error due to external noise, release the chip select (CSB = "H") after every completion of 9-bit data transfer.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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EM65571
130COM/128SEG 65K Color STN LCD Driver
CSB SDA SCL
1 2 3 4 5 6 7 8 9
RS
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. 3-wire Type Serial Interface
7.2 Data Write to Display RAM and Control Register
The data write to display RAM and Control Register use almost the same procedure, only different settings of RS that select access to the object. RS = "L": Display RAM data RS = "H": Control register data In the case of the 80-family MPU, the data is written at the rising edge of WRB. In the case of the 68-family MPU, the data is written at the falling edge of signal E. Data Write Operation
D0~D7 (D0~D15) WRB RS Write Destination Write to Control Register Write to Display RAM
Data0 Data1 Data2 Data3 Data4
Figure 6. Data Write Operation
7.3 Internal Register Read
In the case of display RAM read operation, you need to perform a dummy read one time. The designated address data is not output to read operation immediately after the address is set to AX or AY register, but is output when the second data is read. Dummy read is always required one time after an address set and write cycle. Read Display RAM Operation
WRB D0~D7 (D0~D15) RDB RS
Figure 7. Read Display RAM Operation 20 *
n
Address set (AX,AY) Address = n
***
Dummy Read
n
Data Read Address=n
n+1
Data Read Address=n+1
n+2
Data Read Address=n+2
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver The EM65571 can read the control registers, in case of control register read operation, the data bus upper nibble (D7-D4) is used for register address (0 to FH). A maximum of 16 registers can be accessed directly. Since there are more than 16 registers, the EM65571 has a register bank control. The RE register sets the bank number to be accessed. And the RE address is 0FH, in any bank that can access RE register, 4-steps are needed to read a specific register. 1. Write 04H to the RE register to access the RA register. 2. Write the specific register address to the RA register. 3. Write specific register bank to RE register. 4. Read specific register contents. Register Read Operation
WRB D0~D7 RDB RS
Figure 8. Register Read Operation
04H
addr
bank
Write the Bank number to RE
data
Read a Specific Register
Write the Bank number Write the to RE to access RA Address to RA
7.4 16-Bit Data Access to Display RAM
The EM65571 corresponds to 8-bit and 16-bit bus size access. The data bus size can be selected by the WLS register. WLS = "0": 8-bit bus size WLS = "1": 16-bit bus size In the 16-bit access mode, in accessing the control register, use the low-byte data bus (D7~D0). High byte data bus (D15~D8) are not used in internal circuits when reading the control register using 16-bit bus. Register values are output to D3-D0 and D15-D4 output "H".
7.5 Fast Burst RAM Write Function
The EM65571 has a built-in fast burst RAM write function. The burst mode transfers 32 bits of data in a block at once, so it can decrease half the access time needed for common standard RAM write functions (16 bits data bus). The burst RAM write function is suitable for frequently rewriting data such as displaying color animation.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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EM65571
130COM/128SEG 65K Color STN LCD Driver
Microcontroller Databus [0:15]
EM65571
Internal Buffer 1 Internal Buffer 2 Databus [0:31] 0x00H 0x01H 0x02H 0x03H ....... 2 bytes 2 bytes
Display RAM
Figure 9. Burst RAM Write Operation
7.6 Display Start Address Register
This register determines the Y-address of the display RAM corresponding to the display start line. The display RAM data addressed by the Display Start Address register is output to the common driver start line. The actual common start line of the LCD panel depends on the Display Start Common register and the SHIFT bit of the Display Control register. The registers are preset every time the FLM signal varies in the display line counter. The line counter counts up when synchronized with the LP input and generates line addresses which are read out sequentially as 384 bits of data from display RAM to the LCD driver circuit.
7.7 Display RAM Addressing
The EM65571 has a built-in bit mapped display RAM. The display RAM consists of 2048 bits (16 bits*128) in the X-direction and 128 bits in the Y-direction. In the gradation display mode, the EM65571 provides segment driver output for 48-gradation display using 6 bits. The three outputs of the segment driver can be used for one pixel of RGB. When connected to an STN color LCD panel, the EM65571 can display 128*128 pixels with 65K colors (48 gradation * 48 gradation * 48 gradation). The address area in the X-direction depends on the access bus size. In the X-direction, the X Address register is used to access; and in the Y-direction, the Y Address register is
22 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver used to access. Do not specify any address outside of the effective address area in each access mode because it is not permitted. In Gradation Display Mode (C256="0", 65K="0", 4096 colors) 8-bit Bus Size Access WLS="0", ABS="X",HSW="0" 0H 4-bit 1H 8-bit X-address --------------------------------------------------------------FEH 4-bit FFH 8-bit
0H ---------------7FH
Y-address
4-bit
8-bit
4-bit
8-bit
WLS="0", ABS="X", HSW="1" X-address 0H ---------------7FH 8-bit 8-bit 8-bit 8-bit 16-bit Bus Size Access WLS="1" ABS="0" HSW="X" X-address 0H ---------------7FH 12-bit 12-bit
* 23
0H 8-bit
1H ----------------------------------------------------------------- BEH 8-bit 8-bit
BFH 8-bit
Y-address
0H 12-bit
---------------------------------------------------------------------
7FH 12-bit
Y-address
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver WLS="1" ABS="1" HSW="X" X-address 0H ---------------7FH 12-bit In Gradation Display Mode (C256="1", 65K="0", 256 colors) 8-bit Bus Size Access WLS="0" ABS="X" HSW="X" X-address ---------------------------------------------------------------12-bit 0H ---------------7FH 8-bit 8-bit 8-bit 8-bit 16-bit Bus Size Access WLS="1" ABS="X" HSW="X" 0H 16-bit X-address --------------------------------------------------------------------3FH 16-bit 0H ---------------7FH 16-bit 16-bit 0H 8-bit 1H 8-bit 7EH 8-bit 7FH 8-bit 0H 12-bit --------------------------------------------------------------------7FH 12-bit
Y-address
Y-address
Y-address
24 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver In Gradation Display Mode (C256="0", 65K="1", 65K colors) 8-bit Bus Size Access WLS="0" X-address 0H ---------------7FH 8-bit 8-bit 8-bit 8-bit 16-bit Bus Size Access WLS="1" 0H 16-bit X-address --------------------------------------------------------------------7FH 16-bit 0H ---------------7FH 16-bit 16-bit The addresses, X-address and Y-address can be set up so that they can increment automatically with the address control register. The increment is made every time the display RAM is read from or written to in the MPU. In the Y-direction, 384 bits of data are read out to the display data latch circuit by internal operation when the LP rises in a one-line cycle. They are output from the display data latch circuit when the internal signal LP fails. When internal FLM signals output in one frame cycle are at "H", the values in the display start line register are preset in the line counter and the line counter counts up at the falling edge of the internal signal LP. The display line address counter is synchronized with each timing signal of the LCD system to operate and is independent of the address counters X and Y. The EM65571 has a window area setting command for specified display RAM area access. To use the window function, you need to set up two positions X and Y addresses. You also need to set up the auto increment mode (AXI="1", AYI="1"). Two position means window start position and window end position. The window start position's X and Y-address set to normal the X-address (AX) and Y-address (AY)
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
0H 8-bit
1H ----------------------------------------------------------------- FEH 8-bit 8-bit
FFH 8-bit
Y-address
Y-address
7.8 Display RAM Access Using Windows Function
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EM65571
130COM/128SEG 65K Color STN LCD Driver registers. The window end position's X and Y address set to Window the X-end Address (EX) and Window Y-end Address (EY) register. In window function access, you can modify the write access and set to AIM="1". In the case of using window function access, it should be set to the following registers before accessing the RAM. WIN = "1", AXI="1", AYI="1" X-Address, Y-Address, Window X-end Address, Window Y-end Address Moreover, you should keep the following address conditions: Window end X-address (EX) Window end Y-address (EY) Window start X-address (AX) Window start Y-address (AY) X direction (X,Y) Start Address Y direction Window Access Area (X,Y) End Address
Figure 10. All Display RAM Area
7.9 Display RAM Data and LCD
One bit of display RAM data corresponds to one dot of LCD. Normal display and reverse display by REV register are setup as follows. Normal display (REV=0): RAM data = "0" not lighted RAM data = "1" lighted Reverse display (REV=1): RAM data = "0" lighted RAM data = "1" not lighted
7.10 Segment Display Output Order/Reverse Set up
The order of display output, SEGA0, SEGB0, SEGC0 to SEGA127, SEGB127, and SEGC127 can be reversed. If REF control bit is set to "1", display by reversing access to display the RAM from the MPU by using REF register. This reduces the limitation in placing IC when assembling an LCD panel module.
26 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
7.11 Relationship between Display RAM and Address
The Display RAM Block Diagram is shown in the figure below:
Bit-order reverse Write:depends on REF, SWAP Read:depends on REF
Internal Data Bus Bit Order Reverse
Write Data Read Data
Grayscale Conversion Data Conversion
Segment data
SEGMENT Output I/F Data conversion is dependent on 65K, REF, SWAP, GLSB
Display start address
Effective Y address
MPU I/F
The EM65571 executes address conversion that depends on the control register setting. In case of auto increment mode, usually the AX register is incremented by one. For instance when REF and AXI are both "1", the AX register is incremented by one, but the effective X-address seems to decrement because of address conversion. The effective Y-address use AY register values as it is.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
AY Register
Display RAM
X-Address (00H~FFH)
Effective X-address
Address Conversion Circuit
Address Conversion is dependent on 65K, WLS, REF setting Valid maximum is dependent on 5K, WLS, WIN, HSW, C256 setting
AX Register
Figure 11. Display RAM Block Diagram
LA Register
Y-Address (00H~7FH)
Counter
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EM65571
130COM/128SEG 65K Color STN LCD Driver Gradation Mode (256 Color), (C256=1, 65K=0) (1). 8-bit Mode (WLS=0)
HSW ABS REF * * * * 0 1 SWAP 0 1 D0 D1 D2 X-address / Data Bus / Palette / Palette Bit / Segment Assigned X=00H X=7FH D3 D4 D5 D6 D7 D0 D1 D2 X=7FH X=00H D3 D4 D5 D6 C2 D6 C2 A127 SEG Palette C C1 C3 B3 SEG C127 D4 D5 D7 Palette C C1 C3 B3 D7
Palette C
Palette B
C1
C2
C3
A2
A3
B1
B2
B3
A2
A3
B1 D2 B1
SEG A127
HSW ABS REF SWAP * * * * 0 1 1 0 D0
X-address / Data Bus / Palette / Palette Bit / Segment Assigned X=00H X=7FH D1 D2 D3 D4 D5 D6 D7 D0 D1 X=7FH X=00H D3 B127 SEG B2 Palette B A3
Palette C
Palette A
Palette B
C1
C2
C3
A2
A3
B1
B2
B3
A2
28 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
SEG C127
SEG
SEG
SEG
C0
B0
A0
Palette A
SEG B127
SEG A0
SEG B0
SEG C0
B2
Palette B
Palette A
Palette A
*
*
HSW ABS REF SWAP
HSW ABS REF SWAP
* * * * 1 1 0 0 1 0 SEG A0 SEG B0 SEG C0 SEG A1 SEG B1 SEG C1 SEG A126 SEG B126 SEG C126 X=3FH X=00H SEG A127 SEG B127 Palette C SEG C127 Palette A 1 0 *
*
SEG A1 Palette A Palette B SEG B1 SEG C1 X=00H X=3FH SEG A0 Palette A Palette B SEG B0 SEG C0 SEG A127 Palette A Palette B SEG B127 SEG C127 SEG A126 Palette A Palette B SEG B126 SEG C126 Palette C Palette C Palette C
Product Specification (V1.0) 08.04.2005 X=00H
(2). 16-bit Mode (WLS=1)
X=3FH
(This specification is subject to change without further notice)
A2 A3 B1 B2 B3 C1 C2 C3 A2 A3 B1 B2 B3 C1 C2 C3 A2 A3 B1 B2 B3 C1 C2 C3 A2 A3 B1 B2 B3 C1 C2 C3 Palette A D0 D1 D2 Palette B D3 D4 D5 Palette C D6 D7 D8 Palette A D9 D10 Palette B D11 D12 D13 Palette C D14 D15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
X-address / Data Bus / Palette / Palette Bit / Segment Assigned
X=3FH X=00H
X-address / Data Bus / Palette / Palette Bit / Segment Assigned
130COM/128SEG 65K Color STN LCD Driver
EM65571
* 29
A2 A3 B1 B2 B3 C1 C2 C3 A2 A3 B1 B2 B3 C1 C2 C3
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
A2 A3 B1 B2 B3 C1 C2 C3 A2 A3 B1 B2 B3 C1 C2 C3
D0 D1 D2 Palette B D3 D4 D5 Palette C D6 D7 D8 Palette A D9 D10 Palette B D11 D12 D13 Palette C D14 D15
EM65571
130COM/128SEG 65K Color STN LCD Driver Gradation Mode (4096 Color), (C256=0, 65K=0) (1). 8-bit Mode (WLS="0")
HSW ABS REF SWAP 0 0 * * 0 1 0 1 D0 D1 X=00H X=FEH D2 D3 D0 D1 D2 D3 X-address / Data Bus / Palette / Segment Assigned X=01H X=FFH D4 D5 D6 D7 D0 D1 X=FEH X=00H D2 D3 D0 D1 D2 D3 X=FFH X=01H D4 D5 D5 D1 SEG SEG D3 D4 D7 D0 D6 D6 D2 C127 C127 D3 D7 D7
Palette C
A127
HSW ABS REF SWAP 0 0 * * 0 1 1 0 D0 D1 X=00H X=FEH D2 D3 D0
X-address / Data Bus / Palette / Segment Assigned X=01H X=FFH D1 D2 D3 D4 D5 D6 D7 D0 D1 X=FEH X=00H D2 D3 D0 D1 D2 X=FFH X=01H
Palette C
B127
SEG
SEG
SEG
SEG
SEG
C0
A0
B0
SEG C127
SEG B127
HSW ABS REF SWAP 1 1 * * 0 1 0 1 D0 D1 X=00H X=BEH D2 D3
X-address / Data Bus / Palette / Segment Assigned X=01H X=BFH D5 D6 D7 D0 D1 D2 D3 D0 D1 X=BEH X=00H D2 D3 D4 D5 D6 X=BFH X=01H
D4
Palette C
A127
30 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
B127
SEG
SEG
SEG
SEG
SEG
C0
A0
B0
Palette C
Palette A
Palette B
Palette A
Palette B
SEG A127
SEG C0
SEG B0
SEG A0
Palette C
Palette B
Palette B
Palette A
Palette A
Palette C
Palette A
Palette B
Palette A
Palette B
EM65571
130COM/128SEG 65K Color STN LCD Driver
HSW ABS REF SWAP 1 1 * * 0 1 1 0 D0 D1 X=00H X=BEH D2 D3
X-address / Data Bus / Palette / Segment Assigned X=01H X=BFH D5 D6 D7 D0 D1 D2 D3 D0 D1 X=BEH X=00H D2 D3 D4 D5 D6 D7 X=BFH X=01H D0 D1 D13 D13 SEG D10 D12 SEG D10 D12 D2 D14 D14 C127 * 31 D15 A127 D15 D3
D4
Palette C
C127
(2). 16-bit Mode (WLS="1")
HSW ABS REF SWAP * * 0 0 0 1 0 1 D1 D2 D3 D4 D7 X-address / Data Bus / Palette / Segment Assigned X=00H X=7FH D10 D12 D13 D14 D15 D8 D9 D1 D2 D3 D4 D7 X=7FH X=00H D8 D9
Palette C
B127
SEG
SEG
SEG
SEG
SEG
C0
B0
A0
A127
HSW ABS REF SWAP * * 0 0 0 1 1 0 D1 D2 D3 D4 D7
X-address / Data Bus / Palette / Segment Assigned X=00H X=7FH D10 D12 D13 D14 D15 D8 D9 D1 D2 D3 D4 D7 X=7FH X=00H D8 D9
Palette C
B127
SEG
SEG
SEG
SEG
SEG
C0
A0
B0
SEG C127
SEG B127
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
SEG A127
SEG C0
SEG B0
SEG A0
Palette C
Palette A
Palette B
Palette A
Palette B
Palette C
Palette A
Palette B
Palette A
Palette B
Palette C
Palette A
Palette B
Palette A
Palette B
EM65571
130COM/128SEG 65K Color STN LCD Driver (3). 16-bit Mode (WLS="1")
HSW ABS REF SWAP * * 1 1 0 1 0 1 D0 D1 D2 D3 D4 X-address / Data Bus / Palette / Segment Assigned X=00H X=7FH D10 D11 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 X=7FH X=00H D10 D10 C127 A127 C127 D11 D11 D5 D6 D7 D8 D8 D9 SEG SEG X=FFH X=01H D9 SEG D7
Palette C
A127
HSW ABS REF SWAP * * 1 1 0 1 1 0 D0 D1 D2 D3 D4
X-address / Data Bus / Palette / Segment Assigned X=00H X=7FH D10 D11 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 X=7FH X=00H D5 D6
Palette C
B127
SEG
SEG
SEG
SEG
SEG
C0
A0
B0
C127
Gradation Mode (65K Color), (C256=0, 65K=1) (1). 8-bit Mode (WLS=0)
HSW ABS REF SWA P * * * * 0 1 0 1 X=00H X=FEH X-address / Data Bus / Palette / Segment Assigned X=01H X=FFH X=FEH X=00H
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Palette C
A127
32 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
B127
SEG
SEG
SEG
SEG
SEG
C0
A0
B0
Palette C
Palette A
Palette B
Palette A
Palette B
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
B127
SEG
SEG
SEG
SEG
SEG
C0
B0
A0
Palette C
Palette A
Palette B
Palette A
Palette B
Palette C
Palette A
Palette B
Palette A
Palette B
*
*
*
*
HSW ABS REF SWAP
HSW ABS REF SWAP
HSW ABS REF SWAP
* * * * * * 1 0 1 1 0 0 1 1 0 0 SEG A0 C0 Palette A Palette A SEG 1 0 *
*
SEG
X=00H
X=FEH
Product Specification (V1.0) 08.04.2005 SEG B0 B0 Palette B SEG
C0
Palette A
(2). 16-bit Mode (WLS=1)
SEG
X=00H
X=7FH
X=00H
X=7FH
(This specification is subject to change without further notice)
B0
Palette B
Palette B
X=01H
X=FFH
SEG C0 Palette C
A0
Palette C
SEG
SEG A0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Palette C SEG A127 Palette A SEG C127
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
SEG
X=FEH
C127
Palette A
Palette A
X=00H
SEG B127
X-address / Data Bus / Palette / Segment Assigned
X-address / Data Bus / Palette / Segment Assigned
X=7FH
X=00H
X-address / Data Bus / Palette / Segment Assigned SEG Palette B SEG B127
X=7FH
X=00H
B127
Palette B
Palette B
X=01H
X=FFH
SEG
130COM/128SEG 65K Color STN LCD Driver
EM65571
A127
Palette C
SEG C127
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Palette C
SEG A127
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Palette C
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
* 33
EM65571
130COM/128SEG 65K Color STN LCD Driver Data Read and Write Bit Assignment (1). In 16-bit Data Bus Mode
ABS=0 65K=1 C256=0 Write D15 D14 D13 D12 D11 D10 D9 Read D15 D14 D13 D12 D11 D10 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
ABS=0 65K=0 C256=0 Write D15 D14 D13 D12 D11 D10 D9 Read D15 D14 D13 D12 1 D10 D9
D8 D8
D7 D7
D6 1
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 1
ABS=1 65K=0 C256=0 Write D15 D14 D13 D12 D11 D10 D9 Read 1 1 1 1 D11 D10 D9
D8 D8
D7 D7
D6 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 D0
ABS=
65K=0 C256=1 Write D15 D14 D13 D12 D11 D10 D9 Read D15 D14 D13 D12 D11 D10 D9
D8 D8
D7 D7
D6 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 D0
(2). In 8-bit Data Bus Mode
ABS=* HSW=* 65K=1 C256=0 Address Write Read ABS=* HSW=0 65K=0 C256=0 Address Write Read ABS=* HSW=1 65K=0 C256=0 Address Write Read ABS=* HSW=* 65K=0 C256=1 Address Write Read D7 D7 1 00, 02, 04.........FC, FEH 01, 03, 05.........FD, FFH D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 00, 02, 04.........FC, FEH 1 1 1 01, 03,05.........FD, FFH
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 01, 03, 05.........FD, FFH 1 1 1 1 D3 D2 D1 D0
00, 02, 04.........FC, FEH D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
00, 01, 02.........FD, FE, FFH D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
34 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
7.12 Display Data Structure and Gradation Control
For the purpose of gradation control, one pixel requires multiple bits of display RAM. The EM65571 has 5-bit of data per output to achieve the gradation display. The three outputs of the segment driver are used for one pixel of RGB, and the EM65571 is connected to an STN color LCD panel. It can display 128*128 pixels with 65K colors (5 bits * 6 bits [5+FRC] * 5 bits). In this case, since the gradation display data is processed by a single access to the memory, the data can be rewritten fast and naturally. The weighting for each data bit is dependent on the status of the SWAP bit and the REF bit that is selected when data is written to the display RAM. Gradation Mode (65K Color) 8-bit Mode (REF, SWAP) = (0, 0) or (1, 1)
SEGAi
SEGBi
SEGCi i = 0 to 127 Gradation Palette j = 0 to 47 Gradation Control
Palette Aj
Palette Bj
Palette Cj
1
LSB
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
MSB
Display RAM Data
MSB LSB
MSB LSB
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
MPU Write Data X Address: 2nH, 2n+1H
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Note: Internal X-address
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 35
EM65571
130COM/128SEG 65K Color STN LCD Driver (REF, SWAP) = (0, 1) or (1, 0)
SEGAi SEGBi SEGCi i = 0 to 127
Palette Aj
Palette Bj
Palette Cj
Gradation Palette j = 0 to 47 Gradation Control
1
LSB
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
MSB
Display RAM Data
MSB LSB
MSB LSB
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
MPU W rite Data X Address: 2nH, 2n+1H
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Note: Internal X-address
16-bit Mode In 16-bits access, the weighting for each data bit is dependent on the status of the SWAP bit and the REF bit that is selected when data is written to the display RAM, as in the case with 8-bits access. (REF, SWAP) = (0, 0) or (1, 1)
SEGAi SEGBi SEGCi i = 0 to 127
Palette Aj
Palette Bj
Palette Cj
Gradation Palette j = 0 to 47 Gradation Control
1
LSB
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
MSB
Display RAM Data
MSB LSB
MSB LSB
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D12D13D14 D15 Note: Internal X-address
MPU Write Data X Address: 2nH, 2n+1H
36 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
(REF, SWAP) = (0, 1) or (1, 0)
SEGAi SEGBi SEGCi i = 0 to 127
Palette Aj
Palette Bj
Palette Cj
Gradation Palette j = 0 to 47 Gradation Control
1
LSB
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
MSB
Display RAM Data
MSB LSB
MSB LSB
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
MPU Write Data X Address: 2nH, 2n+1H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Note: Internal X-address
Gradation Mode (4096 Color) 8-bit mode (REF, SWAP)=(0,0) or (1,1)
SEGAi SEGBi SEGCi i=0 to 127
Palette Aj
Palette Bj
Palette Cj
Gadation Palette j = 0 to 15 Gradation Control
0
LSB
0
0
0
1
0
0
0
1
1
1
1
MSB
Display RAM Data
MSB LSB
MSB LSB
0 HSW=1 ABS="X"
0
0
0
1
0
0
0
1
1
1
1 D7 D3
D0 D1 D2 D3 D0 D1 D2 D3 D4 D0 D1 D2 D3 D4 D5 D6 D7 D0
D5 D6 D1 D2
MPU Write Data X Address: 2nH, 2n+1H
Note : Internal X address : 2nH ,2n+1H (REF="0") : (FE-2n)H , [FF-(2n+1)]H (REF="1") In HSW=1, Address=00H~BFH
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 37
EM65571
130COM/128SEG 65K Color STN LCD Driver (REF, SWAP) = (0, 1) or (1, 0)
SEGAi SEGBi SEGCi i=0 to 127
Palette Aj
Palette Bj
Palette Cj
Gradation Palette j = 0 to 15 Gradation Control
0
LSB
0
0
0
1
0
0
0
1
1
1
1
MSB
Display RAM Data
MSB LSB
MSB LSB
0 HSW=1 ABS="X"
0
0
0
1
0
0
0
1
1
1
1
D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3
MPU Write Data X address: 2nH, 2n+1H
Note : Internal X address : 2nH ,2n+1H (REF="0") : (FE-2n)H , [FF-(2n+1)] H (REF="1") In HSW=1, Address=00H~BFH
16-bit mode In 16-bits access, the weighting for each data bit is dependent on the status of the SWAP bit and the REF bit that is selected when data is written to the display RAM, as in the case with 8-bits access. (REF, SWAP)=(0, 0) or (1, 1)
SEGAi SEGBi SEGCi i = 0 to 127
Palette Aj
Palette Bj
Palette Cj
Gradation Palette j = 0 to 15 Gradation Control
0
LSB
0
0
0
1
0
0
0
1
1
1
1
MSB
Display RAM Data
MSB LSB
MSB LSB
0 ABS=1
0
0
0
1
0
0
0
1
1
1
1
D1 D2 D3 D4 D7 D8 D9 D10 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Note : Internal X address : nH (REF="0") HSW="X" : 7FH-nH (REF="1")
38 *
MPU Write Data X address: nH
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver (REF, SWAP)=(0, 1) or (1, 0)
SEGAi SEGBi SEGCi i = 0 to 127
Palette Aj
Palette Bj
Palette Cj
Gradation Palette j = 0 to 15 Gradation Control
0
LSB
0
0
0
1
0
0
0
1
1
1
1
MSB
Display RAM Data
MSB LSB
MSB LSB
0
0
0
0
1
0
0
0
1
1
1
1
D1 D2 D3 D4 D7 D8 D9 D10 D12 D13 D14 D15 ABS=1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Note : Internal X address : nH (REF="0") HSW="X" : 7FH-nH (REF="1")
MPU Write Data X address: nH
Gradation Mode (256 color) 8-bit mode (REF, SWAP) = (0, 0) or (1, 1)
SEGAi
SEGBi
SEGCi i = 0 to 127
Palette Aj
Palette Bj
Palette Cj
Gradation Palette j = 0 to 7 Gradation Control
0 Gradation LSB circuit
0
0
MSB
1
LSB
0
0
MSB
1
LSB
1
1
MSB
Display RAM Data
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
1 D6
1 D7
MPU Write Data X address: nH
Note : Internal X address : nH (REF="0") : 7FH-nH (REF="1")
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 39
EM65571
130COM/128SEG 65K Color STN LCD Driver (REF, SWAP) = (0, 1) or (1, 0)
SEGAi SEGBi SEGCi i=0 to 127
Gradation Palette Gradation Control Display RAM Data MPU Write Data X Address: nH 1
Palette Cj
Palette Bj
Palette Aj
j = 0 to 7
1
1
LSB
0
MSB
0
1
LSB
0
MSB
0
0 Gradation LSB circuit
MSB
1 D0
1 D1
1 D2
0 D3
0 D4
1 D5
0 D6
0 D7
Note : Internal X address : nH (REF="0") : 7FH-nH (REF="1")
16-bit mode (WLS=1) (REF, SWAP) = (0, 0) or (1, 1)
SEGAi SEGBi SEGCi SEGAi+1 SEGBi+1 SEGCi+1 i = 0, 2, 4 to 126
Palette Aj
Palette Bj
Palette Cj
Palette Aj
Palette Bj
Palette Cj
Gradation Palette j = 0 to 7
0 Gradation LSB circuit 0 0
MSB
1
LSB
0
0
MSB
1
LSB
1
1
MSB
0
0
MSB
1
LSB
0
0
MSB
1
LSB
1
1
MSB
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
1 D6
1 D7
0 D8
0 D9
1 D10
0 D11
0 D12
1 D13
1 D14
1 D15
MPU Write Data X address: nH
Note : Internal X address : nH (REF="0") : 3FH-nH (REF="1")
40 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
(REF, SWAP)=(0,1) or (1,0)
SEGAi SEGBi SEGCi SEGAi+1 SEGBi+1 SEGCi+1 i=0, 2, 4 to 126
Gradation palette
Palette Cj
Palette Bj
Palette Aj
Palette Cj
Palette Bj
Palette Aj
j = 0 to 7
Gradation control 0 display RAM data 1 MSB 1 1 LSB 0 MSB 0 1 0 LSB MSB 1 MSB --------------MPU Write Data X address: nH 0 D0 0 D1 1 D2 0 D3 0 D4 1 D5 1 D6 1 D7 0 D8 0 D9 1 D10 0 D11 0 D12 1 D13 1 D14 1 D15 0 1 1 0 LSB MSB 0 1 0 LSB MSB 0 Gradation LSB circuit
Note : Internal X address : nH (REF="0") : 3FH-nH (REF="1")
7.13
Gradation LSB Control
In 256 color mode (C256=1), the EM65571 provides segment driver output for 8-gradation display using 3 bits and for 4-gradation display using 2 bits. The segment driver output for the 4-gradation display uses 2 bits written to the corresponding RAM area and 1 bit supplemented by the gradation LSB circuit, and then selects 4-gradation from 8-gradation. In 256 color mode (C256=1), the segment driver output for the 4-gradation display results in a gradation level of 0 regardless of the gradation LSB when 2 bits of data on the display RAM are "00". When 2-bits of data on the display RAM are "11", a gradation level of 7/7 is selected regardless of the bit information of the gradation LSB. The other gradation levels are selected depending on the 2 bits of data on the display RAM and the gradation LSB bits. One bit of data is supplemented by setting the gradation LSB register (GLSB). The Gradation LSB control bit is applied to all 4-gradation segment drivers. Gradation LSB = "0": Select 0 as the LSB information on the RAM for 4-gradation segment drivers. Gradation LSB = "1": Select 1 as the LSB information on the RAM for 4-gradation segment drivers.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 41
EM65571
130COM/128SEG 65K Color STN LCD Driver
7.14
Gradation Palette
The EM65571 has two gradation display modes, the gradation fixed display mode and the gradation variable display mode. Select either of the two modes using the gradation display mode register. PWM = "0": Select the variable display mode using 32 gradations selected from 48 gradations (65K=1, C256=0). Select the variable display mode using 16 gradations selected from 48 gradations (65K=0, C256=0). Select the variable display mode using 8 gradations selected from 48 gradations (65K=0, C256=1). PWM = "1": Select the fixed display mode using specific 32 gradations (65K=1, C256=0) Select the fixed display mode using specific 16 gradations (65K=0,C256=0) Select the fixed display mode using specific 8 gradations (65K=0,C256=1) To select the best gradation level suited for the LCD panel, use the gradation palette register among the 48-level gradation palettes in the gradation variable display mode. The segment driver output is set up by the selected 32-levels of gradation palettes. The gradation palette register provides three registers for the SEGAi (0-127) group, SEGBi (0-127) group, and SEGCi (0-127) group of segment driver outputs [palettes Aj, Bj, and Cj (j = 0-31)]. Each register consists of a 6-bit register, selecting 32 gradations from the pattern for 48 gradations.
42 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver Initial values on the gradation palette register 65K Color Gradation Mode 65K=1, C256="*" [Three groups of palettes Aj, Bj, and Cj (j = 0-31) are available]
(MSB) RAM Data (LSB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Register Name Palette0 Palette1 Palette2 Palette3 Palette4 Palette5 Palette6 Palette7 Palette8 Palette9 Palette10 Palette11 Palette12 Palette13 Palette14 Palette15 Palette16 Palette17 Palette18 Palette19 Palette20 Palette21 Palette22 Palette23 Palette24 Palette25 Palette26 Palette27 Palette28 Palette29 Palette30 Palette31 Initial Value 000000 000010 000011 000101 000110 001000 001001 001011 001100 001110 001111 010001 010010 010100 010101 010111 011000 011010 011011 011101 011110 100000 100001 100011 100100 100110 100111 101001 101010 101100 101101 101111
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 43
EM65571
130COM/128SEG 65K Color STN LCD Driver 4096 Color Gradation Mode 65K=0, C256=0 [Three groups of palettes Aj, Bj, and Cj (j = 0-15) are available]
(MSB) RAM Data (LSB) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Register Name Palette0 Palette1 Palette2 Palette3 Palette4 Palette5 Palette6 Palette7 Palette8 Palette9 Palette10 Palette11 Palette12 Palette13 Palette14 Palette15 Initial Value 000000 000011 000110 001001 001100 001111 010010 010101 011000 011011 011110 100001 100100 100111 101010 101110
256 Color Mode 65K=0, C256=1 [Three groups of palettes Aj, Bj, and Cj (j = 0-7) are available]
(MSB) RAM Data (LSB) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Register Name Palette0 Palette1 Palette2 Palette3 Palette4 Palette5 Palette6 Palette7 Initial Value 000000 000100 001011 010011 011010 100001 101000 101111
44 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
Gradation level table (PWM = "0", variable mode, 65K= "1", C256="*") [Three groups of palettes Aj, Bj, and Cj (j = 0-31) are available
Palette 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation Level 0 1/48 2/48 3/48 4/48 5/48 6/48 7//48 8/48 9/48 10/48 11/48 12/48 13/48 14/48 15/48 16/48 17/48 18/48 19/48 20/48 21/48 22/48 23/48 Remarks gradation palette0 initial value gradation palette1 initial value gradation palette2 initial value gradation palette3 initial value gradation palette4 initial value gradation palette5 initial value gradation palette6 initial value gradation palette7 initial value gradation palette8 initial value gradation palette9 initial value gradation palette10 initial value gradation palette11 initial value gradation palette12 initial value gradation palette13 initial value gradation palette14 initial value gradation palette15 initial value 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Palette 1100 1100 1101 1101 1110 1110 1111 1111 000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation Level 24/48 25/48 26/48 27/48 28/48 29/48 30/48 31/48 32/48 33/48 34/48 35/48 36/48 37/48 38/48 39/48 40/48 41/48 42/48 43/48 44/48 45/48 46/48 47/48 Remarks gradation palette16 initial value gradation palette17 initial value gradation palette18 initial value gradation palette19 initial value gradation palette20 initial value gradation palette21 initial value gradation palette22 initial value gradation palette23 initial value gradation palette24 initial value gradation palette25 initial value gradation palette26 initial value gradation palette27 initial value gradation palette28 initial value gradation palette29 initial value gradation palette30 initial value gradation palette31 initial value
Gradation level table (PWM = "0", variable mode, 65K= "0", C256="0") [Three groups of palettes Aj, Bj, and Cj (j = 0-15) are available
Palette 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation level 0 1/48 2/48 3/48 4/48 5/48 6/48 7//48 8/48 9/48 10/48 11/48 12/48 13/48 14/48 15/48 16/48 17/48 18/48 19/48 Remarks gradation palette0 initial value 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Palette 1100 1100 1101 1101 1110 1110 1111 1111 000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation level 24/48 25/48 26/48 27/48 28/48 29/48 30/48 31/48 32/48 33/48 34/48 35/48 36/48 37/48 38/48 39/48 40/48 41/48 42/48 43/48 Remarks gradation palette8 initial value
gradation palette1 initial value
gradation palette9 initial value
gradation palette2 initial value
gradation palette10 initial value
gradation palette3 initial value
gradation palette11 initial value
gradation palette4 initial value
gradation palette12 initial value
gradation palette5 initial value
gradation palette13 initial value
gradation palette6 initial value
gradation palette14 initial value * 45
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 20/48 21/48 22/48 23/48 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 44/48 45/48 46/48 47/48
gradation palette7 initial value
gradation palette15 initial value
Gradation level table (PWM = "0", variable mode, 65K= "0", C256="1") [Three groups of palettes Aj, Bj, and Cj (j = 0-7) are available
Palette 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation level 0 1/48 2/48 3/48 4/48 5/48 6/48 7//48 8/48 9/48 10/48 11/48 12/48 13/48 14/48 15/48 16/48 17/48 18/48 19/48 20/48 21/48 22/48 23/48 Remarks gradation palette0 initial value 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Palette 1100 1100 1101 1101 1110 1110 1111 1111 000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation level 24/48 25/48 26/48 27/48 28/48 29/48 30/48 31/48 32/48 33/48 34/48 35/48 36/48 37/48 38/48 39/48 40/48 41/48 42/48 43/48 44/48 45/48 46/48 47/48 Remarks
gradation palette4 initial value
gradation palette1 initial value
gradation palette5 initial value
gradation palette2 initial value
gradation palette6 initial value
gradation palette3 initial value
gradation palette7 initial value
46 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
7.15
Color Display (PWM+FRC)
Display color on the LCD, using gradation level to control th4e RGB color filter. The EM65571 uses 16 bits display data for 65K color. In 16 bits, D0-D4 means 32-gradation levels from 48 gradation levels R (or B), D5-D10 means 32-gradation levels from 48 gradation levels + FRC control bit G, D11-D15 means selecting 32-gradation levels B (or G) from 48 gradation levels. Display RAM data RED, BLUE and Gradation level relationship
R, B Pixel Data 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Output Level GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7 GP8 GP9 GP10 GP11 GP12 GP13 GP14 GP15 R, B Pixel Data 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Output Level GP16 GP17 GP18 GP19 GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP27 GP28 GP29 GP30 GP31
GP: Abbreviation of Gradation Palette
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 47
EM65571
130COM/128SEG 65K Color STN LCD Driver Display Ram Data Green and Gradation Level Relationship When LSB=1, FRC enable, tThe FRC control bit is located at the G pixel data LSB
G Pixel Data 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 Output Level GP0 (GP0+GP1)/2 GP1 (GP1+GP2)/2 GP2 (GP2+GP3)/2 GP3 (GP3+GP4)/2 GP4 (GP4+GP5)/2 GP5 (GP5+GP6)/2 GP6 (GP6+GP7)/2 GP7 (GP7+GP8)/2 GP8 (GP8+GP9)/2 GP9 (GP9+GP10)/2 GP10 (GP10+GP11)/2 GP11 (GP11+GP12)/2 GP12 (GP12+GP13)/2 GP13 (GP13+GP14)/2 GP14 (GP14+GP15)/2 GP15 (GP15+GP16)/2 G Pixel Data 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Output Level GP16 (GP16+GP17)/2 GP17 (GP17+GP18) GP18 (GP18+GP19) GP19 (GP19+GP20) GP20 (GP20+21) GP21 (GP21+GP22) GP22 (GP22+GP23) GP23 (GP23+GP24) GP24 (GP24+GP25) GP25 (GP25+GP26) GP26 (GP26+GP27) GP27 (GP27+GP28) GP28 (GP28+GP29) GP29 (GP29+GP30) GP30 (GP30+GP31) GP31 GP31
GP: Abbreviation of Gradation Palette
48 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
7.16
Display Timing Circuit
The display timing circuit generates internal signals and timing pulses (internal LP, FLM, M) by clock. It can select external input (CK) or internal oscillation.
Symbol LP (internal) FLM (internal) M (internal) Description LP or latched clock signal. At the rising edge, count the display line counter. At the falling edge, output the LCD drive signal. FLM or First Line Maker, signal for LCD display synchronous signals. When FLM is set to "H", the display start-line address is present. Signal for LCD drive output alternated signals.
7.17
Signal Generation to Display Line Counter and Display Data Latching Circuit
Both the clock for the line counter and the clock to display the data latching circuit from the display clock (internal LP) are generated. Synchronized with the display clock (internal LP), the line addresses of the Display RAM are generated and 384-bit display data are latched to display the data latching circuit and output to the LCD drive circuit (segment output). Read-out of the display data to the LCD drive circuit is completely independent of the MPU.
7.18
Generation of the Alternated Signal (internal M) and the Synchronous Signal (internal FLM)
The LCD alternated signal (internal M) and synchronous signal (internal FLM) are generated by the display clock (internal LP). The FLM generates an alternated drive waveform to the LCD drive circuit. Normally, the FLM generates alternated drive waveform every frame (M-signal level is reversed every one frame). However, by setting up data (n-1) in an n-line reverse register and n-line alternated control bit (NLIN) at "1", an n-line reverse waveform is generated.
7.19
Display Data Latching Circuit
The display data latching circuit temporally latches the display data that is output to the LCD driver circuit from the display RAM, once every one common period. Normal display/reverse display, display ON/OFF, and display all on functions are operated by controlling the data in the display data latch, therefore, no data within the display RAM changes.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 49
EM65571
130COM/128SEG 65K Color STN LCD Driver
7.20
Output Timing of the LCD Driver
Display Timing at Normal mode (not reverse mode), 1/128 DUTY. 127 128 1 2 3 128 1 2 3 128 1
LP FLM M V0 V1 COM0 V4 VSS V0 V1 COM1 V4 VSS V0 V2 SEG0 V3 VSS V0 V2 SEG1 V3 V2 V3 VSS V3 V2 V3 V0 V4 V1 V1 V4 VSS
7.21
LCD Driver Circuit
This driver circuit generates four levels of LCD driver voltage. The circuit has 384-segment output and 130-common output and outputs a combined display data and internal signal M. Two of the common outputs, COMA and COMB, are special outputs. The COMA and COMB outputs are not influenced by partial setting, they are mainly used for display. The common driver circuit that has shift register sequentially outputs common scan signals.
50 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
7.22
Oscillator Circuit
The EM65571 has a CR oscillator. The output from this oscillator is used as the timing signal source of the display and the boosting clock for the booster. When external clock is used, feed the clock to CK pin. The duty cycle of the external clock must be 50%. The resistance ratio of the CR oscillator is programmable. If you change this ratio, also change the frame frequency for display.
7.23
Power Supply Circuit
This circuit supplies voltages necessary to drive an LCD. The circuit consists of a booster and a voltage converter. Boosted voltage from the booster is fed to the voltage converter that converts this input voltage into V0, V1, V2, V3 and V4 that are used to drive the LCD. This internal power supply should not be used to drive a large LCD panel containing many pixels. Otherwise, the display quality will degrade considerably. Instead, use an external power supply. When using an external power supply, turn off the internal power supply (AMPON, DCON="00"), disconnect pins CAP1-, CAP1+, CAP2+, CAP2-, CAP3+, CAP4+, CAP5+, CAP6+, VOUT and VEE. Then, feed the external LCD drive voltages to pins V0, V1, V2, V3 and V4. The power circuit can be controlled by a power circuit related register. So, partial function of the built-in power circuit can be used with external power supply.
DCON AMPON Booster Circuit Voltage Conversion Circuit 0 0 1 0 1 1 Disable Disable Enable Disable Enable Enable External Voltage Input V0, V1, V2, V3 and V4 are supplied 1 VOUT is supplied 2 -
Note:
1
When the booster and voltage converter are not operating, disconnect pins CAP+, CAP-, CAP2+, CAP2-, CAP3+, CAP4+, CAP5+, CAP6+, VOUT and VEE. Apply external LCD driver voltages to the corresponding pins. Since the booster is not operating, disconnect pins CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, CAP4+, CAP5+, CAP6+ and VEE. Derive the voltage source to be supplied to the voltage converter from the VOUT pin.
2
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 51
EM65571
130COM/128SEG 65K Color STN LCD Driver
7.24
Booster Circuit
Placing capacitor C1 across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP1-, across CAP4+ and CAP2-, across CAP5+ and CAP1-, across CAP6+ and CAP2-, and across VOUT and VSS will boost the voltage coming from VEE and VSS nth times and outputs the boosted voltage to the VOUT pin. The boosted voltage, either twice, three times, four times or five times the supply voltage and which is output to the VOUT pin is determined by the boost step register, and set by a command instruction. In case the required voltage is twice the voltage supply, this is achieve by placing capacitor C1 only across CAP1+ and CAP1-, and opening CAP2+, CAP2-, CAP3+, CAP1-, CAP4+, CAP2-, CAP5+, CAP1-, CAP6+ and CAP2-. In case the required voltage is three times the voltage supply, this is achieve by placing capacitor C1 across CAP1+ and CAP1-, across CAP2+ and CAP2-, and opening CAP3+, CAP1-, CAP4+, CAP2-, CAP5+, CAP1-, CAP6+ and CAP2-. In case the required voltage is four times the voltage supply, this is achieve by placing capacitor C1 across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP1-, and opening CAP4+, CAP2-, CAP5+, CAP1-, CAP6+ and CAP2-. In case the required voltage is five times the voltage supply, this is achieve by placing capacitor C1 across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP1-, across CAP4+ and CAP2-, and opening CAP5+, CAP1-, CAP6+ and CAP2-. In case the required voltage is six times the voltage supply, this is achieve by placing capacitor C1 across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP1-, across CAP4+ and CAP2-, across CAP5+ and CAP1-, and opening CAP6+ and CAP2-. In case the required voltage is seven times the voltage supply, this is achieve by placing capacitor C1 across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP1-, across CAP4+ and CAP2-, across CAP5+ and CAP1-, across CAP6+ and CAP2-. When using a built-in booster circuit, the output voltage (VOUT) must be less than the recommended operating voltage (20V). If the output voltage (VOUT) is over the recommended operating voltage, the proper and full functionality of the chip cannot be guaranteed. VOUT=20V VOUT=9V VEE=3V VSS=0V 3 times boosting VEE=2.8V VSS=0V 7 times boosting
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
52 *
EM65571
130COM/128SEG 65K Color STN LCD Driver When using 7x boosting ratio, the VEE operating voltage should not exceed 2.8V. For a guaranteed result, the VOUT should be less than the recommended operating voltage of 20V.
7.25
Electronic Volume
The voltage conversion circuit has a built-in electronic volume, which allows the VBA to be controlled with DV register setting. The DV registers are 7 bits, so it's advisable to select 113 voltage values for the VBA voltage. The relationship between VBA and DV is shown in the following equation:
M + Offset VBA = 1 + x VREF 381
where M: DV register value (8~20) Offset: CV1~CV4 setting VREF: Internal temperature compensation output voltage
7.26
Voltage Regulator
The EM65571 has a built-in reference voltage regulator, which generates the voltage amplified by the input voltage from the internal temperature compensation output voltage VREF pin. The generated voltage is output at the V0 pin. Even if the boosted voltage level fluctuates, V0 remains stable as long as VOUT is higher than V0. Stable power supply can be obtained using this constant voltage, even if the load fluctuates. The EM65571 uses the generated V0 level for the reference level of the electronic volume to generate an LCD driver voltage.
7.27
Voltage Generator Circuit
The voltage converter contains the voltage generator circuit. The LCD driver voltages other than V0, which is, V1, V2, V3 and V4 are obtained by dividing V0 through a resistor network. The LCD driver voltage from EM65571 is biased at 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11, 1/12 or 1/13. When using the internal power supply, connect a stabilizing capacitor C2 to each of the pins V0 to V4. The capacitance of C2 should be determined while observing the LCD panel to be used. When using an external power supply, apply external LCD driver voltages to V0, V1, V2, V3, V4, and disconnect pins CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, CAP4+, CAP5+, CAP6+, VOUT, VEE. When using only the voltage conversion circuit, turn off the internal booster circuit, disconnect pins CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, CAP4+, CAP5+, CAP6+ and VEE. Derive the voltage source to be supplied to the voltage converter from the VOUT pin.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 53
EM65571
130COM/128SEG 65K Color STN LCD Driver
VDD VDD VEE VREF VDD VDD VEE VREF CAP5+ CAP1CAP1+ CAP2CAP2+ CAP3+ CAP4+ CAP5+ CAP6+ 0.1 C1 VOUT External V1 Power Supply V2 V3 V4 V0 VOUT V0 V1 V2 V3 V4 vss VSS C1 C1 C1 C1 CAP6+ CAP4+ CAP2CAP2+ VBA VOUT C1 C1 CAP3+ CAP1C1 CAP1+
V0 C1 V1 C1 V2 C1 V3 C1 V4
When using external power supply. Recommended value: C1 = 1 F
When using internal power circuit. (7 times boosting)
Note: External Capacitance must use B characteristic.
54 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
VDD VDD VEE VREF
CAP5+ CAP3+ CAP1CAP1+ CAP6+ CAP4+ CAP2CAP2+
External Power Supply
C1 C1 C1 C1 VSS C1
VOUT V0 V1 V2 V3 V4
When using an internal power circuit and internal reference voltage. (VOUT supplied externally, and not using booster circuit)
Recommended value: C1 = 1F Note: External Capacitance must use B characteristic.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 55
EM65571
130COM/128SEG 65K Color STN LCD Driver
7.28
EEPROM Function
For the EM65571 to support EEPROM function to tune to the LCD operating voltage Vop, first, select EEPROM operating mode, EEPROM power from internal or external, and initial oscillator frequency or faster oscillator frequency (+50%). Select the register (Bank5 [AH]), using (M1, M0) to select the operating mode for the EEPROM, (M1, M0) = 00 Read information from the EEPROM; (M1, M0) = 01 Program information to the EEPROM; (M1, M0) = 10 Erase information on the EEPROM; (M1, M0) = 11 Reserved.
(M1, M0) 00 01 10 11 EEPROM Operating Mode Read Program Erase Reserve
Secondly, the power supply for the EEPROM is selective. By setting the VPP_EXT control bit of the register, you can select internal power (from V0) or external power to support the EEPROM. VPP_EXT=0 internal power; VPP_EXT=1 force 16~18V from the VPP pin externally. Thirdly, you can select the oscillator frequency by setting the OSC control bit of register. OSC=0 initial oscillator frequency setting; OSC=1 oscillator frequency + 50%. You can get Vop calibration offset voltage by setting the Vop calibration offset register.
CV4-CV1 0111 0110 ... 0000 1000 1001 ... 1111 Calibration Offset +7 +6 ... 0 -8 -7 ... -1
M + Offset VBA = 1 + x VREF 381
where M: DV register value Offset: CV1~CV4 setting VREF: internal temperature compensation output voltage
V 0 = VBA x N
where
56 *
N : RM register setting
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver The flow charts for the program, read, and erase EEPROM to get correct Vop offset voltage are shown as follows:
Select CV to get the correct Vop offset Voltage
RD Start : (M1, M0) set 00 Reset
ERASE Start : (M1, M0) set 10 RD Start : (M1, M0) set 00
Delay < 10 RD Start : (M1, M0) set 00 WR Start : (M1, M0) set 01 RD End: (M1, M0) set 11 Delay < 10 us Delay 10*N ms
RD End : (M1, M0) set 11 Delay 10xN ms
Delay<10 s
ERASE End: (M1, M0) set 11
RD End: (M1, M0) set 11 WR End: (M1, M0) set 11
Read EEPROM Data to CV4~CV1
Reset
Get the correct Vop offset Voltage
CV4~CV1=1111
Program Program
Read
Erase
For example, the desired Vop calibration offset is +7, CV4~CV1 is set to 0111, the example code is shown below: WRITE #F5H WRITE #B7H // set RE FLAG 101 INSTRUCTION Bank 5 // set CV4~CV1=0111
WRITE #A4H // set EEPROM operating mode programming ; EEPROM power is from the internal V0 ; oscillator frequency is the initially set value DELAY 10*N MS // wait for 10*N ms to finish programming WRITE #ACH WRITE #F0H WRITE #B1H WRITE #F5H // set EEPROM mode reserve (finish programming) // set RE FLAG 000 INSTRUCTION Bank 0 // EM65571 reset // set RE FLAG 101 INSTRUCTION Bank 5
* 57
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver WRITE #A0H // set EEPROM operating mode reading ; read data from EEPROM to CV4~CV1 register
DELAY <10 S // wait <10 S to finish reading WRITE #ACH // set EEPROM mode reserve (finish reading data from EEPROM to CV4~CV1 register)
Read WRITE #F5H // set RE FLAG 101 INSTRUCTION Bank 5
WRITE #D1H // EXTENSION COMMAND WRITE #A0H DELAY >10 S WRITE #ACH // set EEPROM operating mode reading // wait <10 s to finish reading // set EEPROM mode reserve (finish reading)
WRITE #D0H // EXTENSION COMMAND WRITE #A0H DELAY >10 S WRITE #ACH Erase WRITE #F5H WRITE #A8H // set RE FLAG 101 INSTRUCTION Bank 5 // set EEPROM operating mode erasing ; erase EEPROM data to 1 // set EEPROM operating mode reading ; read data from EEPROM to CV4~CV1 register. // wait <10 s to finish reading // set EEPROM mode reserve (finish reading)
DELAY 10*N MS // wait 10*N ms to finish erasing WRITE #ACH WRITE #F0H WRITE #B1H WRITE #F5H WRITE #A0H // set EEPROM mode reserve (finish erasing) // set RE FLAG 000 INSTRUCTION Bank 0 // EM65571 reset // set RE FLAG 101 INSTRUCTION Bank 5 // set EEPROM operating mode reading ; read data from EEPROM to CV4~CV1 register
DELAY <10 S // wait <10 S to finish reading WRITE #ACH // set EEPROM mode reserve (finish reading data from EEPROM to CV4~CV1 register)
(CV4~CV1 should be equal to 1111 after erasing)
58 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
7.29 Partial Display Function
The EM65571 has a partial display function, which can display a part of the graphic display area. This function is used to set the lower bias ratio, lower boost step, and lower LCD drive voltage. In setting the partial display function, the EM65571 provides low power consumption, hence, it is most suitable for clock indication or calendar indication of portable devices. ELAN LCD DRIVER Low Power and Low Voltage Normal Display LCD DRIVER
Partial Display
Figure 12. Partial Display Image
When using the partial display function, it is necessary to keep the following sequence.
Any Display Condition Display Off (ON/OFF= "0") Power circuit Off (DCON= "0", AMPON= "0") WAIT
Set Power Function * Set Boost step * Set Electronic Volume * Set Bias Ratiot
Power Circuit On (DCON= "1", AMPON= "1") WAIT
Setting Display Function * Set Duty Ratio * Display Start Address * Display start common
Display on (ON/OFF= "1") Partial Display
Select a display duty ratio for the partial display from 1/10 to 1/128 using the DS (LCD duty ratio) register. Set the most suitable values for LCD drive bias ratio, LCD drive voltage, electronic volume, the number of boosting steps, and other details according to the actual LCD panel used and the selected duty ratio.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 59
EM65571
130COM/128SEG 65K Color STN LCD Driver
7.30
Discharge Circuit
The EM65571 has a built-in discharge circuit, which discharges electricity from capacitors for stability of power sources (V0~V4). The discharge circuit is valid, while the DIS register is set to "1". When the built-in power supply is used, it should be set DIS="1" after the power source is turned off (DCON, AMPON) = (0, 0). Both the built-in power source and the external power source (V0~V4, VOUT) should not be turned off while DIS= "1".
7.31
Initialization
Setting RESB pin to "L" initializes the EM65571. Normally, the RESB pin is initialized together with the MPU by connecting to the reset pin of the MPU. When power is ON, be sure to make RESB="L".
ITEM Display RAM X Address Y Address Display starting line Display ON/OFF Display Normal/Reverse Display duty n-line alternate (BF1, BF0) Common shift direction Increment mode REF mode Data SWAP Mode Register in electronic volume Power Supply Display mode Bias ratio Gradation Palette 0 Gradation Palette 1 Gradation Palette 2 Gradation Palette 3 Gradation Palette 4 Gradation Palette 5 Gradation Palette 6 Gradation Palette 7 Gradation Palette 8 COM0 Initial Value Not fixed 00H set 00H set Set at the first line (0H) Display OFF Normal 1/10 Every frame unit (0, 0) COM127, COMA, COMB Increment OFF Normal OFF (0, 0, 0, 0, 0, 0, 0) OFF Gradation display mode 1/13 bias (0, 0, 0, 0, 0, 0) (0, 0, 0, 0, 1, 0) (0, 0, 0, 0, 1, 1) (0, 0, 0, 1, 0, 1) (0, 0, 0, 1, 1, 0) (0, 0, 1, 0, 0, 0) (0, 0, 1, 0, 0, 1) (0, 0, 1, 0, 1, 1) (0, 0, 1, 1, 0, 0) Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
60 *
EM65571
130COM/128SEG 65K Color STN LCD Driver
ITEM Gradation Palette 9 Gradation Palette 10 Gradation Palette 11 Gradation Palette 12 Gradation Palette 13 Gradation Palette 14 Gradation Palette 15 Gradation Palette 16 Gradation Palette 17 Gradation Palette 18 Gradation Palette 19 Gradation Palette 20 Gradation Palette 21 Gradation Palette 22 Gradation Palette 23 Gradation Palette 24 Gradation Palette 25 Gradation Palette 26 Gradation Palette 27 Gradation Palette 28 Gradation Palette 29 Gradation Palette 30 Gradation Palette 31 Gradation display mode Gradation LSB RAM access data length Discharge Register
Initial Value (0, 0, 1, 1, 1, 0) (0, 0, 1, 1, 1, 1) (0, 1, 0, 0, 0, 1) (0, 1, 0, 0, 1, 0) (0, 1, 0, 1, 0, 0) (0, 1, 0, 1, 0, 1) (0, 1, 0, 1, 1, 1) (0, 1, 1, 0, 0, 0) (0, 1, 1, 0, 0, 1) (0, 1, 1, 0, 1, 1) (0, 1, 1, 1, 0, 1) (0, 1, 1, 1, 1, 0) (1, 0, 0, 0, 0, 0) (1, 0, 0, 0, 0, 1) (1, 0, 0, 0, 1, 1) (1, 0, 0, 1, 0, 0) (1, 0, 0, 1, 1, 0) (1, 0, 0, 1, 1, 1) (1, 0, 1, 0, 0, 1) (1, 0, 1, 0, 1, 0) (1, 0, 1, 1, 0, 0) (1, 0, 1, 1, 0, 1) (1, 0, 1, 1, 1, 1) Variable mode 0 8-bit mode 0
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 61
EM65571
130COM/128SEG 65K Color STN LCD Driver
7.32
Precautionary Measures during Power ON and Power OFF
High current that may flow if a voltage is supplied to the LCD driver power supply while the system power supply is floating may permanently damage this LSI. The details are as follows.
7.32.1 When Using an External Power Supply
Procedure for Power ON o Logic system (VDD) power ON, make reset operation. o Supply external LCD driver voltage to corresponding pins (V0, V1, V2, V3 and V4) Procedure for Power OFF o Set HALT register to "1" or initiate a reset operation. o Cut off external LCD driver voltage. o Logic system (VDD) power OFF. Note: Connect a serial resistor (50 to 100) or fuse to the LCD driver power V0 or VOUT (when using only an internal voltage conversion circuit) of the system as a current limiter. Moreover, set up suitable resistor values corresponding to the LCD display grade.
7.32.2
When Using a Built-in Power Supply
Procedure for Power ON o Logic system (VDD) power ON o Booster circuit system (VEE) power ON o Initiate a reset operation, enable booster and voltage conversion circuit. If the VDD and VEE voltages are not of the same potential, turn on the power logic system (VDD) first. Procedure for Power OFF o Set the HALT register to "1" or reset the system. o Booster circuit system (VEE) power OFF. o Logic system (VDD) power OFF. If VDD and VEE are not of the same potential, turn off the VEE first. After VEE, VOUT, V0, V1, V2, V3 and V4 voltages are below LCD ON voltage (threshold voltage for Liquid crystal turn on), power off the logic system (VDD).
7.32.3
Power Supply Rising Time
Though especially there is no constraint on the rising time of the power supply, the "tr" (rising time) of the following is recommended in the practical use.
VDD, VEE tr
62 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
Item tr Recommended Rising Time 30s ~ 10ms Applicable Power VDD, VEE
Note: The rising time is the time from 10% of VDD/VEE to 90%.
7.33
Example of Register Setting
7.33.1 Initialization
Power ON (VDD, VEE - VSS) Power Stabilization RESET WAIT
Setting the Operational Functions * Set the Electrical Volume * Set the Bias Ratio
Setting the Operational Functions * Set the Power Control (DCON = "1", AMPON = "1")
End of Initialization
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 63
EM65571
130COM/128SEG 65K Color STN LCD Driver
7.33.2
Display Data
End of Initialization
Setting the Operational Functions * Set the display start address * Set the address increment control * Set the X-address * Set the Y-address
Setting the Operational Functions * Write the Display Data
Setting the Operational Functions * Set the Display on/off control (ON/OFF= "1")
End of Display Data Setting
7.33.3
Power OFF
Any Condition
Setting the Operational Functions * Set HALT= "1" or initiate a reset operation (LCD driver output VSS level) * Set DIS= "1" (Discharge V0-V4 capacitor)
WAIT
Power OFF ( VEE, VDD)
64 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
8
Control Register
8.1 Control Register
Control Register Table (Bank 0)
Control Register X Address (Lower nibble) X Address (Upper nibble) Y Address (Lower nibble) Y Address (Upper nibble) Display start address (Lower nibble) Display start address (Upper nibble) n-line altemation (Lower nibble) n-line altemation (Upper nibble) Display control (1) [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] Pins (for 80-family) & Bank Address & Code D2 AX2 AX6 AY2 AY6 LA2 LA6 N2 N6 D1 AX1 AX5 AY1 AY5 LA1 LA5 N1 N5 Function Set of X direction Address AX0 in display RAM Set of X direction Address AX4 in display RAM Set of Y direction Address AY0 in display RAM Set of Y direction Address AY4 in display RAM Set address of display RAM LA0 making common starting line display Set address of display RAM LA4 making common starting line display Set the number of altemated N0 reverse line Set the number of altemated N4 reverse line SHIFT: Select common shift direction 65K: Select 65K gradation ON/ ALLON: All display ON OFF ON/OFF: Display ON/OFF control REV: Display normal/reverse NLIN: n line reverse control SWAP: Display data swapping REF REF: Seqment normal/reverse WIN: Select window. AIM: Select increment mode AXI AYI: Y increment, AXI: X increment AMPON: Internal AMP. ON HALT: Power saving DCON: Boosting circuit ON ACL ACL: Resetting Set LCD drive duty ratio DS0 Set number of boosting step for VU0 booster circuit Set bias ratio B0 for LCD driving voltage TST0: for LS1 test,must set to "0" RE0 RE: set register bank number D0 CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 AX3 1 AX7 0 AY3 1 AY7 0 LA3 1 LA7 0 N3 1 N7
[8H] Display control (2)
0
1
0
1
0
0
0
1
0
0
SHI 0 FT
65K
ALL ON
[9H] Increment control [AH] Power control
0
1
0
1
0
0
0
1
0
0
SW 1 REV NLIN AP
0
1
0
1
0
0
0
1
0
1
0 WIN AIM
AYI
[BH] LCD Duty Ratio [CH] Booster [DH] Bias ratio control [EH] Register Access Control [FH]
0 0 0 0 0
1 1 1 1 1
0 0 0 0 0
1 1 1 1 1 0/1
0 0 0 0 0/1
0 0 0 0 0/1
0 0 0 0
1 1 1 1 1
0 1 1 1 1
1 0 0 1 1
AMP HA 1 ON LT 0 DS3 DS2 1 SHP VU2 0 B3 TS 1 T0 B2 RE2
DC ON DS1 VU1 B1 RE1
Note: The asterisk "*" mark means "don't care" Parentheses [ ] shows the control register address.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 65
EM65571
130COM/128SEG 65K Color STN LCD Driver Control Register Table (Bank 1)
Control Register
Gradation Palette A0,A8,A16,A24
Pins (for 80-family) & Bank Address & Code CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] [8H] [9H] [AH] [BH] [CH] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
D0
Function Set the umber of
Gradation Palette A0,A8,A16,A24
(Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble)
0 PAX.3 PAX.2 PAX.1 PAX.0 1* * PAX.5 PAX.4
Gradation Palette A0,A8,A16,A24 Gradation Palette A1,A9,A17,A25
Set the umber of
Gradation Palette A0,A8,A16,A24
Set the umber of 0 PAX.3 PAX.2 PAX.1 PAX.0 1* * PAX.5 PAX.4
Gradation Palette A1,A9,A17,A25
Gradation Palette A1,A9,A17,A25 Gradation Palette A2,A10,A18,A26
Set the umber of
Gradation Palette A1,A9,A17,A25
Set the umber of 0 PAX.3 PAX.2 PAX.1 PAX.0 1* * PAX.5 PAX.4
Gradation Palette A2,A10,A18,A26
Gradation Palette A2,A10,A18,A26 Gradation Palette A3,A11,A19,A27
Set the umber of
Gradation Palette A2,A10,A18,A26
Set the umber of 0 PAX.3 PAX.2 PAX.1 PAX.0 1* * PAX.5 PAX.4
Gradation Palette A3,A11,A19,A27
Gradation Palette A3,A11,A19,A27 Gradation Palette A4,A12,A20,A28
Set the umber of
Gradation Palette A3,A11,A19,A27
Set the umber of 0 PAX.3 PAX.2 PAX.1 PAX.0 1* * PAX.5 PAX.4
Gradation Palette A4,A12,A20,A28
Gradation Palette A4,A12,A20,A28 Gradation Palette A5,A13,A21,A29
Set the umber of
Gradation Palette A4,A12,A20,A28
Set the umber of 0 PAX.3 PAX.2 PAX.1 PAX.0 1* * PAX.5 PAX.4
Gradation Palette A5,A13,A21,A29
Gradation Palette A5,A13,A21,A29 Gradation Palette A6,A14,A22,A30
Set the umber of
Gradation Palette A5,A13,A21,A29
Set the umber of 0 PAX.3 PAX.2 PAX.1 PAX.0 1* TS 1 T0 * RE2 PAX.5 PAX.4 RE1 RE0
Gradation Palette A6,A14,A22,A30
Gradation Palette A6,A14,A22,A30
Set the umber of
Gradation Palette A6,A14,A22,A30
(Upper nibble) [DH] Register Access Control [FH]
TST0: for LS1 test,must set to "0 RE: set register bank number
Note: The asterisk "*" mark means "don't care" Parentheses [ ] shows the control register address.
Control Register Table (Bank 2)
Control Register
Gradation Palette A7,A15,A23,A31
Pins (for 80-family) & Bank Address & Code CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] [8H] [9H] [AH] [BH] [CH] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
D0
Function Set the umber of
(Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble)
Gradation Palette A7,A15,A23,A31 Gradation Palette B0,B8,B16,B24 Gradation Palette B0,B8,B16,B24 Gradation Palette B1,B9,B17,B25 Gradation Palette B1,B9,B17,B25 Gradation Palette B2,B10,B18,B26 Gradation Palette B2,B10,B18,B26 Gradation Palette B3,B11,B19,B27 Gradation Palette B3,B11,B19,B27 Gradation Palette B4,B12,B20,B28 Gradation Palette B4,B12,B20,B28 Gradation Palette B5,B13,B21,B29 Gradation Palette B5,B13,B21,B29
(Upper nibble) [DH] Register Access Control [FH]
0 PAX.3 PAX.2 PAX.1 PAX.0 Gradation Palette A7,A15,A23,A31 Set the umber of 1* * PAX.5 PAX.4 Gradation Palette A7,A15,A23,A31 Set the umber of 0 PBX.3 PBX.2 PBX.1 PBX.0 Gradation Palette B0,B8,B16,B24 Set the umber of 1* * PBX.5 PBX.4 Gradation Palette B0,B8,B16,B24 Set the umber of 0 PBX.3 PBX.2 PBX.1 PBX.0 Gradation Palette B1,B9,B17,B25 Set the umber of 1* * PBX.5 PBX.4 Gradation Palette B1,B9,B17,B25 Set the umber of 0 PBX.3 PBX.2 PBX.1 PBX.0 Gradation Palette B2,B10,B18,B26 Set the umber of 1* * PBX.5 PBX.4 Gradation Palette B2,B10,B18,B26 Set the umber of 0 PBX.3 PBX.2 PBX.1 PBX.0 Gradation Palette B3,B11,B19,B27 Set the umber of 1* * PBX.5 PBX.4 Gradation Palette B3,B11,B19,B27 Set the umber of 0 PBX.3 PBX.2 PBX.1 PBX.0 Gradation Palette B4,B12,B20,B28 Set the umber of 1* * PBX.5 PBX.4 Gradation Palette B4,B12,B20,B28 Set the umber of 0 PBX.3 PBX.2 PBX.1 PBX.0 Gradation Palette B5,B13,B21,B29 Set the umber of 1* * PBX.5 PBX.4 Gradation Palette B5,B13,B21,B29 TS TST0: for LS1 test,must set to "0 1 T0 RE2 RE1 RE0 RE: set register bank number
Note: The asterisk "*" mark means "don't care" Parentheses [ ] shows the control register address.
66 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver Control Register Table (Bank 3)
Control Register
Gradation Palette B6,B14,B22,B30
Pins (for 80-family) & Bank Address & Code CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] [8H] [9H] [AH] [BH] [CH] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0/1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 PBX.3 PBX.2 PBX.1 1* * PBX.5
D0
Function Set the umber of
(Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble)
Gradation Palette B6,B14,B22,B30 Gradation Palette B7,B15,B23,B31
0 PBX.3 PBX.2 PBX.1 1* * PBX.5
Gradation Palette B7,B15,B23,B31 Gradation Palette C0,C8,C16,C24
0 PCX.3 PCX.2 PCX.1 1* * PCX.5
Gradation Palette C0,C8,C16,C24 Gradation Palette C1,C9,C17,C25
0 PCX.3 PCX.2 PCX.1 1* * PCX.5
Gradation Palette C1,C9,C17,C25 Gradation Palette C2,C10,C18,C26
0 PCX.3 PCX.2 PCX.1 1* * PCX.5
Gradation Palette C2,C10,C18,C26 Gradation Palette C3,C11,C19,C27
0 PCX.3 PCX.2 PCX.1 1* * PCX.5
Gradation Palette C3,C11,C19,C27 Gradation Palette C4,C12,C20,C28
0 PCX.3 PCX.2 PCX.1 1* TS 1 T0 * RE2 PCX.5 RE1
Gradation Palette C4,C12,C20,C28
(Upper nibble) [DH] Register Access Control [FH]
PBX.0 Gradation Palette B6,B14,B22,B30 Set the umber of PBX.4 Gradation Palette B6,B14,B22,B30 Set the umber of PBX.0 Gradation Palette B7,B15,B23,B31 Set the umber of PBX.4 Gradation Palette B7,B15,B23,B31 Set the umber of PCX.0 Gradation Palette C0,C8,C16,C24 Set the umber of PCX.4 Gradation Palette C0,C8,C16,C24 Set the umber of PCX.0 Gradation Palette C1,C9,C17,C25 Set the umber of PCX.4 Gradation Palette C1,C9,C17,C25 Set the umber of PCX.0 Gradation Palette C2,C10,C18,C26 Set the umber of PCX.4 Gradation Palette C2,C10,C18,C26 Set the umber of PCX.0 Gradation Palette C3,C11,C19,C27 Set the umber of PCX.4 Gradation Palette C3,C11,C19,C27 Set the umber of PCX.0 Gradation Palette C4,C12,C20,C28 Set the umber of PCX.4 Gradation Palette C4,C12,C20,C28 TST0: for LS1 test,must set to "0 RE0 RE: set register bank number
Note: The asterisk "*" mark means "don't care" Parentheses [ ] shows the control register address.
Control Register Table (Bank 4)
Control Register
Gradation Palette C5,C13,C21,C29
Pins (for 80-family) & Bank Address & Code CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 [0H] [1H] [2H] [3H] [4H] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0/1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 PCX.3 PCX.2 1* *
D0
Function Set the umber of
(Lower nibble) (Upper nibble) (Lower nibble) (Upper nibble) (Lower nibble)
Gradation Palette C5,C13,C21,C29 Gradation Palette C6,C14,C22,C30
0 PCX.3 PCX.2 1* *
Gradation Palette C6,C14,C22,C30 Gradation Palette C7,C15,C23,C31
0 PCX.3 PCX.2 1* 0 SC3 1* 0 PWM 1 C256 0 DV3 1* 0 RA3 1* 0 BF1 TS 1 T0 * SC2
*
Gradation Palette C7,C15,C23,C31
(Upper nibble) [5H] Display start common [6H] Temperature Compensation [7H] Display Select Control [8H] RAM Data length Set [9H] Electronic Volume (Lower nibble) [AH] Electronic Volume (Upper nibble) [BH] Register read Control [CH] Select Rf [DH] Extended Power Control [EH] Register Access Control [FH]
GL SB HSW DV2 DV6 RA2 RF2 BF0 RE2
PCX.1 PCX.0 Gradation Palette C5,C13,C21,C29 Set the umber of PCX.5 PCX.4 Gradation Palette C5,C13,C21,C29 Set the umber of PCX.1 PCX.0 Gradation Palette C6,C14,C22,C30 Set the umber of PCX.5 PCX.4 Gradation Palette C6,C14,C22,C30 Set the umber of PCX.1 PCX.0 Gradation Palette C7,C15,C23,C31 Set the umber of PCX.5 PCX.4 Gradation Palette C7,C15,C23,C31 Set Common Driver SC1 SC0 Start Line Temperature Compensation set TCS1 TCS0 Select Plane(access/display)
Select PWM Mode
PS1 ABS DV1 DV5 RA1 RF1 HPM RE1
PS0 WLS DV0 DV4 RA0
Set GLSB Bit. Set Data length on RAM Access 8-bit access or 16-bit access Set Electronic Vollume Register (lower code) Set Electronic Vollume Register (upper code) Set Register Address for read Select Rf ratio of OSC circuit
RF0 DIS RE0 Discharge capacitance of V0,V1,V2,V3,V4 Pins TST0: for LS1 test,must set to "0 RE: set register bank number
Note: The asterisk "*" mark means "don't care". Parentheses [ ] shows the control register address.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 67
EM65571
130COM/128SEG 65K Color STN LCD Driver Control Register Table (Bank 5)
Control Register Window X End Address (Lower nibble) Window X End Address (Upper nibble) Window Y End Address (Lower nibble) Window Y End Address (Upper nibble) Start Address for line reverse (Lower nibble) Start Address for line reverse (Upper nibble) End Address for line reverse (Lower nibble) End Address for line reverse (Upper nibble) Line reverse control Burst RAM write control Reverse type Regulator multiple ratio Control Register EEPROM mode select register [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] Pins (for 80-family) & Bank Address & Code CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 D0 Function Set X end address for window function access Set X end address for window function access Set Y end address for window function access Set Y end address for window function access Set start line for line reverse display Set start line for line reverse display 1 LS7 LS6 LS5 LS4 Set end line for line reverse display 0 LE3 LE2 LE1 LE0 Set end line for line reverse display 1 LE7 LE6 LE5 LE4 LR EV BST: Burst RAM write ON / OFF BT: Reverse type select LREV: Line reverse control
0 EX3 EX2 EX1 EX0 1 EX7 EX6 EX5 EX4 0 EY3 EY2 EY1 EY0 1 EY7 EY6 EY5 EY4 0 LS3 LS2 LS1 LS0
[8H] [9H]
0 0
1 1
0 0
1 1
1 1
0 0
1 1
1 1
0 0
0 0
0* 1*
BST BT
[AH] Vop calibration offset register [BH] Register Access Control [FH]
0 0 0
1 1 1
0 0 0
1 1 1 0/1
1 1 0/1
0 0 0/1
1 1
1 1 1
0 0 1
1 1 1
0 M1
RM2 RM1 RM0 set regulator multiple ratio M1,M0:EEPROM mode select VPP_ VPP_EXT:EEPROM power select M0 EXT OSC OSC:oscillator frequency select set Vop offset voltage TST0:for LS1 test,must set to "0" RE:set register bank number
1 CV4 CV3 CV2 CV1 TS 1 T0 RE2 RE1 RE0
Note: The asterisk "*" mark means "don't care" Parentheses [ ] shows the control register address. Address [CH], [DH], [EH] in Bank 5 of the control register are reserved.
8.2 Control Register Functions
The EM65571 has many control registers. In case of control register access, the upper nibble of the data bus (D7~D4) represents the register address, the lower nibble of the data bus (D3~D0) represents the data. The access example is shown in the following. The Pins (CSB, RS, RDB, WRB) setting is for the 80-family MPU interface. Only the setting of the terminal (RDB, WRB) is different, when it is accessed by the 68-family MPU. Example: X Address
D7 0 D6 0 D5 0 D4 0 D3 AX3 D2 AX2 D1 AX1 D0 AX0 CSB 0 RS 1 RDB 1 WRB 0 RE2 0 RE1 0 RE0 0
Register address
Data
Pins setting
Register Bank
In writing to the control register, direct addressing to D7~D4 of the data bus can be used. In case of a register read, first set the RA register for a specific register address, next read that specific register. Therefore, two steps are needed to perform a register read. Then, specific register output to D3~D0 of the data bus. Except for D3~D0 of the data bus, all are "H". Access to undefined register address area is not allowed. When RS is "L", all read/write operations are accessible in the display RAM. The data bus does not include the register address. In case of a write operation, D3~D0 data is written to the register designated at D7~D4 at the rising edge of the WRB signal. In
68 * Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver case of a read, a register can output to the data bus in RDB active period. The control register and display RAM have equal access time.
8.2.1 X-address Register (AX)
D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0 AX3 AX2 AX1 AX0
Note: During a reset: {AX3, AX2, AX1, AX0} = 0H, read address: 0H
D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0
AX7 AX6 AX5 AX4
Note: During a reset: {AX7, AX6, AX5, AX4} = 0H, read address: 1H The AX register is set to X-address of the display RAM. Data setting is divided into the lower nibble and the upper nibble or 4-bit each.
8.2.2 Y-Address Register (AY)
D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0 AY3 AX2 AY1 AY0
Note: During a reset: {AY3, AY2, AY1, AY0} = 0H, read address: 2H
D7 0 D6 0 D5 1 D4 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0
AY7 AY6 AY5 AY4
Note: During a reset: {AY7, AY6, AY5, AY4} = 0H, read address: 3H The AY register is set to Y-address of the display RAM. Data setting is divided into the lower nibble and the upper nibble or 4-bit each. Addresses 00H to 7FH corresponds to AY7 to AY0, and (NO AND operation) 80H to FFH are reserved but the addresses for (AY7 to AY0) = A0H, A1H are in the display RAM area for icon display.
8.2.3 Display Start Address Register (LA)
D7 0 D6 1 D5 0 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0 LA3 LA2 LA1 LA0
Note: During a reset: {LA3, LA2, LA1, LA0}=0H, read address: 4H
D7 0 D6 1 D5 0 D4 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0
LA7 LA6 LA5 LA4
Note: During a reset: {LA7, LA6, LA5, LA4}=0H, read address: 5H
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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130COM/128SEG 65K Color STN LCD Driver The LA register indicate first the output segment data in the display RAM. This segment data output to the common line is indicated by the SC register. After that the output common line is incremented.
LA7 0 0 LA6 0 0 LA5 0 0 LA4 0 0 : 0 1 1 1 1 1 1 1 127 LA3 0 0 LA2 0 0 LA1 0 0 LA0 0 1 Line Address 0 1
8.2.4 n-line Alternate Register (N)
D7 0 D6 1 D5 1 D4 0 D3 N3 D2 N2 D1 N1 D0 N0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 0
Note: During a reset: {N3, N2, N1, N0} = 0H, read address: 6H
D7 0 D6 1 D5 1 D4 1 D3 N7 D2 N6 D1 N5 D0 N4 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0
Note: During a reset: {N6, N5, N4} = 0H, read address: 7H The reverse line number of the LCD alternate driver is required to be set in the register. The line number has a limit, which must be kept between 2 to 127 lines. The value set up by the alternate register is enabled when NLIN control bit is "1". When NLIN control bit is "0", the alternate driver waveform reverses each frame that is generated.
N7 0 0 N6 0 0 N5 0 0 N4 0 0 N3 0 0 N2 0 0 N1 0 0 N0 0 1 Line Address 2
0
1
1
1
1
1
1
0
127
Alternate Timing (i) NLIN = "0" (in case of 1/128 DUTY Display)
1st Line 2nd Line 3rd Line 127th Line 128th Line 1st Line
LP
FLM M
70 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
(ii) NLIN = "1"
nth line Cycle
1st Line 2nd Line
3rd Line
nth Line
1st Line
2nd Line
LP
M
8.2.5 Display Control (1) Register
D7 D6 D5 D4 1 0 0 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0 SHIFT 65K ALLON ON/OFF
Note: During a reset: {SHIFT, 65K, ALLON, ON/OFF} = 4H, read address: 8H
Various display controls are set up. ON/OFF To control display ON/OFF ON/OFF = "0": Display OFF ON/OFF = "1": Display ON ALLON Regardless of the data for display, all is on. This control has priority over display normal/reverse commands. ALLON = "0": Normal display ALLON = "1": All display lighted 65K Select 65K gradation display 65K="0": 4096 or 256 gradation display, decided by C256 control bit. 65K="1": 65K gradation display mode. SHIFT The shift direction of display scanning data in the common driver output is selected. SHIFT = "0": COM0 COM127 shift-scan SHIFT = "1": COM127 COM0 shift-scan
8.2.6 Display Control (2) Register
D7 D6 D5 D4 1 0 0 1 D3 REV D2 NLIN D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0 SWAP REF
Note: During a reset: {REV, NLIN, SWAP, REF} = 0H, read address: 9H
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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EM65571
130COM/128SEG 65K Color STN LCD Driver Various display controls are set up. REF When the MPU accesses the display RAM, the X address and data can reverse. The REF function is shown in the table below:
REF Access from the MPU X Address D7-D0 D0(LSB) 0 NH D7(MSB) NH (MSB) SEG(8*NH+7)Output Internal Access X Address D7-D0 (LSB) Corresponding Segment Output SEG(8*NH)Output
D0(LSB) 1 NH D7(MSB) MaxH-NH
(MSB) (LSB)
SEG(8*(maxH-NH)+7)Output SEG(8*(maxH-NH))Output
Note: maxH: The maximum X-address in each access mode. The order of segment driver output can be reversed by the register, by register setting, thus lessening the limitations in placing the IC during an LCD module assembly. NLIN The NLIN control n-line alternate driver. NLIN = "0": n-line alternate driver OFF. In each frame, the alternate signals (M) are reversed. NLIN ="1": n-line alternate driver ON. Alternate is performed in accordance to data set up in the n-line alternate register. SWAP When data are written to the display RAM, the bit order of the written data are exchanged. SWAP = "0": Normal mode SWAP = "1": In data writing, bit order is exchange. Example of exchanged bit order
Write Data SWAP = 0 SWAP = 1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
Internal Data
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
8-bit Access (HSW=1)
Write Data SWAP = 0 SWAP = 1 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Internal Data
d0 d1 d2 d3 d4 d5 d6 d7 d7 d6 d5 d4 d3 d2 d1 d0
72 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
16-bit access (HSW=1)
Write Data SWAP=0 SWAP=1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D12D13D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D12D13D14D15
Internal Data
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12d13d14d15 d15 d14 d13 d11 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d12 d10
CAUTION: REF and SWAP should both be set to "1" When data is written to the display RAM, the written data is in normal bit order. When data is read from the display RAM, the bit order of the read data is exchanged. REV In accordance to the of display RAM data, the lighting or not-lighting of the display is set up. REV ="0": When RAM data is at "H", the LCD voltage is ON (normal) REV ="1": When RAM data is at "L", the LCD voltage is ON (reversed)
8.2.6 Increment Control Register Set
D7 1 D6 0 D5 1 D4 0 D3 D2 D1 AYI D0 AXI CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 0 WIN AIM
(During a reset: {WIN, AIM, AYI, AXI} = 0H, read address: AH) This register controls the increment mode and window function when accessing the display RAM. The increment operation of AX and AY registers can be controlled by AIM, AYI and AXI registers setting and every write access or every read access to the display RAM. The AY register directly connects to the display RAM as Y address. The AX register connects to the address converter, and outputs to the display RAM as X address in the auto-increment mode, the AX and AY register are then incremented, but not directly increment the X and Y addresses. In setting the control register, the address increment operation can be made without setting successive addresses for writing data to the display RAM or reading data from the MPU. The WIN register is used for window function control. WIN="0": Normal RAM access WIN="1": Window function access In the case of accessing the window function, the following register should be set before accessing the RAM. WIN="1", AXI="1", AYI="1" X-address, Y-address, Window X End Address, Window Y End Address Moreover, the following address condition should be kept: Window end X address Window end Y address Window start X address Window start Y address
Refer to "6-7 Display RAM access using Window Function" for details on window function.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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130COM/128SEG 65K Color STN LCD Driver
The increment control of X and Y-addresses by AIM, AYI and AXI registers are as follows.
AIM 0 1 Address Increment Timing When writing to or reading from the Display RAM. This is effective when accessing successive address areas. Only when writing to the Display RAM. This is effective the case of "Read Modify Write" AXI 0 1 0 1 Select Address Increment Operation Address is not incremented X-Address is incremented Y-Address is incremented X and Y both are incremented Remark (1) (2) (3) (4)
AYI 0 0 1 1
(1) Regardless of AIM, no increment for AX and AY register. (2) Basing on the set-up of the AIM, automatically change the X-address. In accordance with the REF register, the AX register and X-address becomes as follows.
REF 0 Transition of AX Register 00H 01H ....... max Transition of X Address Same as AX register max maxH ..... 00H
1
Note: maxH: internal maximum X-address in each access mode. (3) Basing on the set-up of the AIM, automatically change the Y-address. Regardless of REF, increment by looping.
Transition of AY Register 00H 01H ....... 7FH Transition of Y Address Same as AY register
(4) According to the set-up of the AIM, simultaneously change the X and Y-address. When the X-address exceeds maxH, the Y-address incremented.
REF 0 Transition of AX and AY Register AX: AY: 1 00H 00H max AX: max maxH AY: Same as AY register 00H Transition of X and Y Address Same as AX and AY register
When each AX exceed maxH, increment AY
00H
00H
7FH
Note: maxH: The internal maximum X-address in each access mode. Following shows address increment in window function access.
74 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
REF 0 Transition of AX and AY Register AX: START START END Address Address+1 Address AY: When each AX exceed AE, increment AY START START Address Address+1 END Address AX: maxHmaxHmaxH(START (START (END Address) Address+1) Address) AY: Same as AY register Transition of X and Y Address Same as AX and AY register
1
Note: maxH: The internal maximum X-address in each access mode. In each operation mode, the following increment operation is performed: (i) When gradation display mode, 8-bit access is selected Address is incremented as described above. (ii) When in gradation display mode and 16-bit access are selected: Accessing the RAM once, accesses two bytes. The X-addresses increment in the order of 00H, 01H,...3EH, and 3FH.
8.2.7 Power Control Register
D7 1 D6 0 D5 1 D4 1 D3 D2 D1 D0 ACL CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0 AMPON HALT DCON
(During a reset: {AMPON, HALT, DCON, ACL} = 0H, read address: BH) ACL The internal circuit can be initialized. ACL = "0": Normal operation ACL = "1": Initialization ON When a reset operation begins internally after the ACL register is set to "1", the ACL register is automatically cleared to "0". An internal reset signal is generated by a clock (built-in oscillation circuit or CK input) for the display. Hence, include a WAIT period for the display clock for at least two cycles. After a WAIT period, proceed with the next operation. DCON The internal booster circuit is set ON/OFF DCON = "0": Booster circuit OFF DCON="1": Booster circuit ON HALT The conditions of power saving are set ON/OFF by this command. HALT = "0": Normal operation HALT="1": Power-saving operation When setting in the power-saving state, the consumed current can be reduced to a value near to the standby current. The internal conditions at power saving are as follows. a. The oscillating circuit and power supply circuit are stopped. b. The LCD driver is stopped, and output of the segment driver and common driver are VSS level. c. The clock input from the CK pin is inhibited. d. The contents of the Display RAM data are maintained. e. The operational mode maintains the state of command execution before executing power saving command.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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130COM/128SEG 65K Color STN LCD Driver AMPON Command The internal OP-AMP circuit block (voltage regulator, electronic volume, and voltage conversion circuit) is set ON/OFF by this command. AMPON = "0": The internal OP-AMP circuit OFF AMPON = "1": The internal OP-AMP circuit ON
8.2.8 LCD Duty (DS)
D7 1 D6 1 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 0 DS3 DS2 DS1 DS0
Note: During a reset: {DS3, DS2, DS1, DS0} = 0H, read address: CH The DS register is set to LCD display duty.
DS3 0 0 0 0 0 0 0 0 1 1 1 1 1 DS2 0 0 0 0 1 1 1 1 0 0 0 0 1 DS1 0 0 1 1 0 0 1 1 0 0 1 1 1 DS0 0 1 0 1 0 1 0 1 0 1 0 1 1 Display Width and Duty 8-dot width display in Y-direction, 1/10 duty 16-dot width display in Y-direction, 1/18 duty 24-dot width display in Y-direction, 1/26 duty 32-dot width display in Y-direction, 1/34 duty 48-dot width display in Y-direction, 1/50 duty 64-dot width display in Y-direction, 1/66 duty 72-dot width display in Y-direction, 1/74 duty 80-dot width display in Y-direction, 1/82 duty 96-dot width display in Y-direction, 1/98 duty 104-dot width display in Y-direction, 1/106 duty 112-dot width display in Y-direction, 1/114 duty 120-dot width display in Y-direction, 1/122 duty 128-dot width display in Y-direction, 1/130 duty
Partial display can be made possible by setting an arbitrary duty ratio.
8.2.9 Booster Setup (VU)
D7 1 D6 1 D5 0 D4 0 D3 * D2 D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 0 VU2 VU1 VU0
Note: During a reset: {VU2, VU1, VU0} = 0H, read address: DH The asterisk "*" mark means "Don't care" The booster steps setting for the VU register
VU2 0 0 0 0 1 1 1 1 76 * VU1 0 0 1 1 0 0 1 1 VU0 0 1 0 1 0 1 0 1 Booster Operation Booster disable (No operation) 2 times voltage output 3 times voltage output 4 times voltage output 5 times voltage output 6 times voltage output 7 times voltage output Prohibit code Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
8.2.10 Bias Setting Register (B)
D7 1 D6 1 D5 1 D4 0 D3 B3 D2 B2 D1 B1 D0 B0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 0
Note: During a reset: {B3, B2, B1, B0} = 0H, read address: EH This register is used to set the bias ratio. A bias ratio can be selected from 1/5 to 1/13 by setting B3, B2, B1, and B0.
B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bias 1/5 Bias 1/6 Bias 1/7 Bias 1/8 Bias 1/9 Bias 1/10 Bias 1/11 Bias 1/12 Bias 1/13 Bias Prohibit code Prohibit code Prohibit code Prohibit code Prohibit code Prohibit code Prohibit code
8.2.11 Register Access Control
D7 1 D6 1 D5 1 D4 0 D3 TST0 D2 RE2 D1 RE1 D0 RE0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0/1 0/1 0/1
Note: During a reset: {TST0, RE2, RE1, RE0} = 0H, read address: FH The RE register is use set to number of register bank. In accessing each control register, set the RE register first. The TST0 register is use for testing purposes, hence, this register must be set to "0"
8.2.13 Gradation Palette Register (PA0~PA7, PB0~PB7, PC0~PC7)
D7 D6 0 0 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1 PAX.3 PAX.2 PAX.1 PAX.0
Note: Read address: 0H X= 0, 8, 16, or 24
D7 0 D6 0 D5 0 D4 1 D3 * D2 * D1 D0/ CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1
PAX.5 PAX.4
Note: Read address: 1H X= 0, 8, 16, or 24 During a reset: PA04~PA00 = "00000" The asterisk "*" mark means "Don't care"
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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130COM/128SEG 65K Color STN LCD Driver
D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 1
PAX.3 PAX.2 PAX.1 PAX.0
Note: Read address: 2H X= 1, 9, 17, or 25
D7 0 D6 0 D5 1 D4 1 D3 * D2 * D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1
PAX.5 PAX.4
Note: Read address: 3H X= 1, 9, 17, or 25 During a reset: PA14~PA10 = "00101") The asterisk "*" mark means "Don't care"
D7 0 D6 1 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1
PAX.3 PAX.2 PAX.1 PAX.0
Note: Read address: 4H X= 2, 10, 18, or 26
D7 0 D6 1 D5 0 D4 1 D3 * D2 * D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 1
PAX.5 PAX.4
Note: Read address: 5H X= 2, 10, 18, or 26 During a reset: PA24~PA20 = "01010" The asterisk "*" mark means "Don't care"
D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1
PAX.3 PAX.2 PAX.1 PAX.0
Note: Read address: 6H X= 3, 11, 19, or 27
D7 0 D6 1 D5 1 D4 1 D3 * D2 * D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1
PAX.5 PAX.4
Note: Read address: 7H X= 3, 11, 19, or 27 During a reset: PA34~PA30 = "01110" The asterisk "*" mark means "Don't care"
D7 1 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1
PAX.3 PAX.2 PAX.1 PAX.0
Note: Read address: 8H X= 4, 12, 20, or 28
D7 1 D6 0 D5 0 D4 1 D3 * D2 * D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1
PAX.5 PAX.4
Note: Read address: 9H X= 4, 12, 20, or 28 During a reset: PA44~PA40 = "10001" The asterisk "*" mark means "Don't care"
78 * Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
D7 1
D6 0
D5 1
D4 0
D3
D2
D1
D0
CSB 0
RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1
PAX.3 PAX.2 PAX.1 PAX.0
Note: Read address: AH X= 5, 13, 21, or 29
D7 1 D6 0 D5 1 D4 1 D3 * D2 * D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1
PAX.5 PAX.4
Note: Read address: BH X= 5, 13, 21, or 29 During a reset: PA54~PA50 = "10101" The asterisk "*" mark means "Don't care"
D7 1 D6 1 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1
PAX.3 PAX.2 PAX.1 PAX.0
Note: Read address: CH X= 6, 14, 22, or 30
D7 1 D6 1 D5 0 D4 1 D3 * D2 * D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 1
PAX.5 PAX.4
Note: Read address: DH X= 6, 14, 22, or 30 During a reset: PA64~PA60 = "11010" The asterisk "*" mark means "Don't care"
D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 1 0
PAX.3 PAX.2 PAX.1 PAX.0
Note: Read address: 0H X= 7, 15, 23, or 31
D7 0 D6 0 D5 0 D4 1 D3 * D2 * D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 1 0
PAX.5 PAX.4
Note: Read address: 1H X= 7, 15, 23, or 31 During a reset: PA74~PA70 = "11111" The asterisk "*"mark means "Don't care"
D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 1 0
PBX.3 PBX.2 PBX.1 PBX.0
Note: Read address: 2H X= 0, 8, 16, or 24
D7 0 D6 0 D5 1 D4 1 D3 * D2 * D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 1 0
PBX.5 PBX.4
Note: Read address: 3H X= 0, 8, 16, or 24 During a reset: PB04~PB00 = "00000" The asterisk "*" mark means "Don't care"
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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130COM/128SEG 65K Color STN LCD Driver
D7 0
D6 1
D5 0
D4 0
D3
D2
D1
D0
CSB 0
RS RDB WRB RE2 RE1 RE0 1 1 0 0 1 0
PBX.3 PBX.2 PBX.1 PBX.0
Note: Read address: 4H X= 1, 9, 17, or 25
D7 0 D6 1 D5 0 D4 1 D3 * D2 * D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 1 0
PBX.5 PBX.4
Note: Read address: 5H X= 1, 9, 17, or 25 During a reset: PB14~PB10 = "00101" The asterisk "*" mark means "Don't care"
D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 1 0
PBX.3 PBX.2 PBX.1 PBX.0
Note: Read address: 6H X= 2, 10, 18, or 26 D7 D6 D5 D4 D3 D2
0 1 1 1 * *
D1
PBX.5
D0
PBX.4
CSB RS RDB WRB RE2 RE1 RE0
0 1 1 0 0 1 0
Note: Read address: 7H X= 2, 10, 18, or 26 During a reset: PB24~PB20 = "01010" The asterisk "*" mark means "Don't care" D7 D6 D5 D4
1 0 0 0
D3
D2
D1
D0
CSB RS RDB WRB RE2 RE1 RE0
0 1 1 0 0 1 0
PBX.3 PBX.2 PBX.1 PBX.0
Note: Read address: 8H X= 3, 11, 19, or 27 D7 D6 D5 D4
1 0 0 1
D3
D2
D1
D0
CSB RS RDB WRB RE2 RE1 RE0
0 1 1 0 0 1 0
PBX.5 PBX.4
Note: Read address: 9H X= 3, 11, 19, or 27 During a reset: PB34~PB30 = "01110" The asterisk "*" mark means "Don't care" D7 D6 D5 D4
1 0 1
D3
D2
D1
D0
CSB
0
RS RDB WRB RE2 RE1 RE0
1 1 0 0 1 0
0 PBX.3 PBX.2 PBX.1 PBX.0
Note: Read address: AH X= 4, 12, 20, or 28 D7 D6 D5 D4 D3 D2
1 0 1 1 * *
D1
D0
CSB RS RDB WRB RE2 RE1 RE0
0 1 1 0 0 1 0
PBX.5 PBX.4
Note: Read address: BH X= 4, 12, 20, or 28 During a reset: PB44~PB40 = "10001") The asterisk "*" mark means "Don't care"
80 * Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
D7 D6 D5 D4
1 1 0 0
D3
D2
D1
D0
CSB
0
RS RDB WRB RE2 RE1 RE0
1 1 0 0 1 0
PBX.3 PBX.2 PBX.1 PBX.0
Note: Read address: CH X= 5, 13, 21, or 29 D7 D6 D5 D4 D3 D2
1 1 0 1 * *
D1
D0
CSB RS RDB WRB RE2 RE1 RE0
0 1 1 0 0 1 0
PBX.5 PBX.4
Note: Read address: DH X= 5, 13, 21, or 29 During a reset: PB54~PB50 = "00101" The asterisk "*" mark means "Don't care" D7 D6 D5 D4
0 0 0 0
D3
D2
D1
D0
CSB RS RDB WRB RE2 RE1 RE0
0 1 1 0 0 1 1
PBX.3 PBX.2 PBX.1 PBX.0
Note: Read address: 0H X= 6, 14, 22, or 30 D7 D6 D5 D4 D3 D2
0 0 0 1 * *
D1
PBX.5
D0
PBX.4
CSB RS RDB WRB RE2 RE1 RE0
0 1 1 0 0 1 1
Note: Read address: 1H X= 6, 14, 22, or 30 During a reset: PB64~PB60 = "11010" The asterisk "*" mark means "Don't care"
D7 D6 D5 D4 0 0 1 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
PBX.3 PBX.2 PBX.1 PBX.0
Note: Read address: 2H X= 7, 15, 23, or 31
D7 0 D6 1 D5 0 D4 1 D3 * D2 * D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
PBX.5 PBX.4
Note: Read address: 3H X= 7, 15, 23, or 31 During a reset: PB74~PB70 = "11111" The asterisk "*" mark means "Don't care"
D7 D6 D5 D4 0 1 0 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
PCX.3 PCX.2 PCX.1 PCX.0
Note: Read address: 4H X= 0, 8, 16, or 24
D7 0 D6 1 D5 0 D4 1 D3 * D2 * D1 PCX.5 D0 PCX.4 CSB 0 RS 1 RDB WRB 1 0 RE2 RE1 RE0 0 1 1
Note: Read address: 5H X= 0, 8, 16, or 24 During a reset: PC04~PC00 = "00000" The asterisk "*" mark means "Don't care"
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Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
D7 D6 D5 D4 0 1 1 0
D3
D2
D1
D0
CSB 0
RS 1
RDB WRB RE2 RE1 RE0 1 0 0 1 1
PCX.3 PCX.2 PCX.1 PCX.0
Note: Read address: 6H X= 1, 9, 17, or 25
D7 0 D6 1 D5 1 D4 1 D3 * D2 * D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
PCX.5 PCX.4
Note: Read address: 7H X= 1, 9, 17, or 25 During a reset: PC14~PC10 = "00101" The asterisk "*" mark means "Don't care"
D7 D6 D5 D4 1 0 0 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
PCX.3 PCX.2 PCX.1 PCX.0
Note: Read address: 8H X= 2, 10, 18, or 26
D7 D6 1 0 D5 D4 D3 D2 0 1 D1 PCX.5 D0 PCX.4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
Note: Read address: 9H X= 2, 10, 18, or 26 During a reset: PC24~PC20 = "01010" The asterisk "*" mark means "Don't care"
D7 D6 D5 D4 1 0 1 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
PCX.3 PCX.2 PCX.1 PCX.0
Note: Read address: AH X= 3, 11, 19, or 27
D7 1 D6 0 D5 1 D4 1 D3 * D2 * D1 PCX.5 D0 PCX.4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
Note: Read address: BH X= 3, 11, 19, or 27 During a reset: PC34~PC30 = "01110" The asterisk "*" mark means "Don't care"
D7 D6 D5 D4 1 1 0 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 1 0 0 RE1 1 RE0 1
PCX.3 PCX.2 PCX.1 PCX.0
Note: Read address: CH X= 4, 12, 20, or 28
D7 1 D6 1 D5 D4 D3 0 1 * D2 * D1 PCX.5 D0 PCX.4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 1 1
Note: Read address: DH = 4, 12, 20, or 28 During a reset: PC44~PC40 = "10001" The asterisk "*" mark means "Don't care"
82 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
D7 D6 D5 D4 0 0 0 0
D3
D2
D1
D0
CSB 0
RS 1
RDB WRB RE2 1 0 1
RE1 0
RE0 0
PCX.3 PCX.2 PCX.1 PCX.0
Note: Read address: 0H X= 5, 13, 21, or 29
D7 0 D6 0 D5 0 D4 1 D3 * D2 * D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
PCX.5 PCX.4
Note: Read address: 1H X= 5, 13, 21, or 29 During a reset: PC54~PC50 = "10101" The asterisk "*" mark means "Don't care"
D7 D6 D5 D4 0 0 1 0 D3 PCX.3 D2 PCX.2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
PCX.1 PCX.0
Note: Read address: 2H X= 6, 14, 22, or 30
D7 0 D6 0 D5 1 D4 1 D3 * D2 * D1 PCX.5 D0 PCX.4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
Note: Read address: 3H X= 6, 14, 22, or 30 During a reset: PC64~PC60 = "11010" The asterisk "*" mark means "Don't care"
D7 D6 D5 D4 0 1 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
0 PCX.3 PCX.2 PCX.1 PCX.0
Note: Read address: 4H X= 7, 15, 23, or 31
D7 0 D6 1 D5 0 D4 1 D3 D2 D1 PCX.5 D0 PCX.4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
Note: Read address: 5H X= 7, 15, 23, or 31 During a reset: PC74~PC70 = "11111" The asterisk "*" mark means "Don't care"
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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EM65571
130COM/128SEG 65K Color STN LCD Driver These gradation palette registers set up the gradation level. The EM65571 has 48 gradation levels. Gradation level table (PWM = "0", variable mode, 65K= "1", C256="*") [Three groups of Palettes Aj, Bj, and Cj (j = 0-31) are available
Palette 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 Gradation Level 0 1/48 2/48 3/48 4/48 5/48 6/48 7//48 8/48 9/48 10/48 11/48 12/48 13/48 14/48 15/48 16/48 17/48 18/48 19/48 20/48 21/48 22/48 23/48 Remarks Palette Gradation Level 24/48 25/48 26/48 27/48 28/48 29/48 30/48 31/48 32/48 33/48 34/48 35/48 36/48 37/48 38/48 39/48 40/48 41/48 42/48 43/48 44/48 45/48 46/48 47/48 Remarks Gradation Palette16 Initial Value Gradation Palette17 Initial Value Gradation Palette18 Initial Value Gradation Palette19 Initial Value Gradation Palette20 Initial Value Gradation Palette21 Initial Value Gradation Palette22 Initial Value Gradation Palette23 Initial Value Gradation Palette24 Initial Value Gradation Palette25 Initial Value Gradation Palette26 Initial Value Gradation Palette27 Initial Value Gradation Palette28 Initial Value Gradation Palette29 Initial Value Gradation Palette30 Initial Value Gradation Palette31 Initial Value
Gradation Palette0 Initial Value 0 1 1 0 0 0 0 11 0 0 1 Gradation Palette1 Initial Value 0 1 1 0 1 0 Gradation Palette2 Initial Value 0 1 1 0 1 1 0 111 0 0 Gradation Palette3 Initial Value 0 1 1 1 0 1 Gradation Palette4 Initial Value 0 1 1 1 1 0 011111 Gradation Palette5 Initial Value 1 0 0 0 0 Gradation Palette6 Initial Value 1 0 0 0 0 1 100010 Gradation Palette7 Initial Value 1 0 0 0 1 1 Gradation Palette8 Initial Value 1 0 0 1 0 0 100101 Gradation Palette9 Initial Value 1 0 0 1 1 0 Gradation Palette10 Initial Value 1 0 0 1 1 1 101000 Gradation Palette11 Initial Value 1 0 1 0 0 1 Gradation Palette12 Initial Value 1 0 1 0 1 0 1 0 1 0 11 Gradation Palette13 Initial Value 1 0 1 1 0 0 Gradation Palette14 Initial Value 1 0 1 1 0 1 1 0 111 0 Gradation Palette15 Initial Value 1 0 1 1 1 1
84 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
Gradation level table (PWM = "0", variable mode, 65K= "0", C256="0") [Three groups of Palettes Aj, Bj, and Cj (j = 0-15) are available
Palette 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation Level 0 1/48 2/48 3/48 4/48 5/48 6/48 7//48 8/48 9/48 10/48 11/48 12/48 13/48 14/48 15/48 16/48 17/48 18/48 19/48 20/48 21/48 22/48 23/48 Remarks Gradation Palette0 Initial Value 0 0 0 Gradation Palette1 Initial Value 0 0 0 Gradation Palette2 Initial Value 0 0 1 Gradation Palette3 Initial Value 1 1 1 Gradation Palette4 Initial Value 1 1 1 Gradation Palette5 Initial Value 1 1 1 Gradation Palette6 Initial Value 1 1 1 Gradation Palette7 Initial Value 1 1 1 Palette 11000 11001 11010 11011 11100 11101 11110 11111 0000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Gradation Level 24/48 25/48 26/48 27/48 28/48 29/48 30/48 31/48 32/48 33/48 34/48 35/48 36/48 37/48 38/48 39/48 40/48 41/48 42/48 43/48 44/48 45/48 46/48 47/48 Remarks Gradation Palette8 Initial Value
Gradation Palette9 Initial Value
Gradation Palette10 Initial Value
Gradation Palette11 Initial Value
Gradation Palette12 Initial Value
Gradation Palette13 Initial Value
Gradation Palette14 Initial Value
Gradation Palette15 Initial Value
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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130COM/128SEG 65K Color STN LCD Driver
Gradation level table (PWM = "0", variable mode, 65K= "0", C256="1") [Three groups of Palettes Aj, Bj, and Cj (j = 0-7) are available
Palette 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation Level 0 1/48 2/48 3/48 4/48 5/48 6/48 7//48 8/48 9/48 10/48 11/48 12/48 13/48 14/48 15/48 16/48 17/48 18/48 19/48 20/48 21/48 22/48 23/48 Remarks Gradation Palette0 Initial Value 0 0 0 0 Gradation Palette1 Initial Value 0 0 0 0 1 1 1 Gradation Palette2 Initial Value 1 1 1 1 1 1 1 1 Gradation Palette3 Initial Value 1 1 1 1 1 Palette 1100 1100 1101 1101 1110 1110 1111 1111 000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gradation Level 24/48 25/48 26/48 27/48 28/48 29/48 30/48 31/48 32/48 33/48 34/48 35/48 36/48 37/48 38/48 39/48 40/48 41/48 42/48 43/48 44/48 45/48 46/48 47/48 Remarks
Gradation Palette4 Initial Value
Gradation Palette5 Initial Value
Gradation Palette6 Initial Value
Gradation Palette7 Initial Value
86 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
8.2.14 Display Start Common
D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 1 0 1 RE1 0 RE0 0 SC3 SC2 SC1 SC0
Note: During a reset:{ SC2, SC1, SC0} = 0H, read address: 6H The SC register set up the scanning start output of the common driver.
SC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Display Starting Common when SHIFT=0 COM0~ COM10~ COM20~ COM30~ COM40~ COM50~ COM60~ COM70~ COM80~ COM90~ COM100~ COM110~ COM120~ COM119~ COM109~ COM99~ COM89~ COM79~ COM69~ COM59~ COM49~ COM39~ COM29~ COM19~ COM9~ Display Starting Common when SHIFT=1
Note: SHIFT="0": COM0 to COM127 shift-scan SHIFT="1": COM127 down to COM0 shift-scan
8.2.15 Temperature Compensation Set
D7 0 D6 1 D5 1 D4 1 D3 * D2 * D1 TCS1 D0 TCS0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 0
Note: During a reset:{ TCS1,TCS0 } = 0H, read address: 7H The asterisk "*" mark means "Don't care"
TCS1 0 0 1 1 TCS0 0 1 0 1 Temperature Compensation Slope -0.05% per C -0.1% per C -0.15% per C -0.2% per C
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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EM65571
130COM/128SEG 65K Color STN LCD Driver The VREF (T) (Temperature compensation output voltage) is controlled by TCS1, TCS0 and the previous environment temperature T.
VREF (T ) = VREF 0 [1 + TCS (25C - T )]
TCS is selected by TCS1 and TCS0, VREF0 = 1.5V at 25C
LCD Driving Voltage
TCS: 00 -0.05% / TCS: 01 -0.1% / TCS: 10 -0.15% / TCS: 11 -0.2% /
Temperature
Figure 11 Temperature Compensation Slope
8.2.16 Display Select Control
D7 D6 D5 D4 1 0 0 0 D3 D2 D1 D0 PS0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0 PWM GLSB PS1
Note: During a reset: {PWM, GLSB} = 0H, read address: 8H) GLSB In 256 color mode, for the segment driver of 4-gradation display, select 4 gradations from 8 gradations using the 2 bits written to the corresponding RAM area and the 1 bit supplemented by the gradation LSB circuit. Supplement the 1 bit of data by setting the gradation LSB register (GLSB). Gradation LSB = "0": Selects 0 as the LSB information on the RAM for 4-gradation segment driver. Gradation LSB = "1": Selects 1 as the LSB information on the RAM for 4-gradation segment driver. PS1, PS0 In 65K color mode, select the 48 gradation level from the 32 gradation palette. In 4096-color mode, select the 16 gradation level from the 32 gradation palette. In 256 color mode, just select a setting lower than 8 gradation.
PS1, PS0 (0, 0) (0, 1) (1, 0) (1, 1) 88 * Selected Palette PaletteX0~PaletteX7 PaletteX8~PaletteX15 PaletteX16~PaletteX23 PaletteX24~PaletteX31
*X: A, B or C
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver PWM The PWM register selects the gradation display mode. PWM = "0": Variable display mode using 32 gradations selected from 48 gradations in 65K color mode (65K=1, C256="*") Variable display mode using 16 gradations selected from 48 gradations in 4096 color mode (65K=0, C256=0) Variable display mode using 8 gradations selected from 48 gradations in 256 color mode (65K=0, C256=1) PWM = "1": 32-gradation fixed display mode
8.2.17 Data Bus Size Select
D7 D6 D5 D4 1 0 0 1 D3 D2 D1 ABS D0 WLS CSB 0 RS 1 RDB 1 WRB 0 RE2 RE1 RE0 1 0 0 C256 HSW
Note: During a reset: {C256, HSW, ABS, WLS} = 0H, read address: 9H WLS The WLS register selects a data bus size in accessing the MPU WLS = "0": The data bus size is 8-bit width WLS = "1": The data bus size is 16-bit width When an MPU access to the control register used 16-bit bus size, high byte data is ignored. ABS ABS= "0": normal mode ABS= "1": change corresponding bit from input data bus HSW HSW="0": High speed writing mode off HSW="1": High speed writing mode on accessing the 8-bit data RAM C256 C256= "0": 4096-color mode C256= "1": 256-color mode *IF 65K=1, C256 is prohibited control bit.
8.2.18 Electronic Volume Register
D7 1 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB 1 0 RE2 RE1 RE0 1 0 0 DV3 DV2 DV1 DV0
Note: Read address: AH
D7 1 D6 0 D5 1 D4 1 D3 * D2 D1 D0 CSB 0 RS 1 RDB 1 WRB 0 RE2 RE1 RE0 1 0 0
DV6 DV5 DV4
Note: Read address: BH During a reset: {DV6~DV0} = 00H The asterisk "*" mark means "Don't care"
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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EM65571
130COM/128SEG 65K Color STN LCD Driver The DV register can control the VBA voltage. The DV register has 7 bits, so a 113 level voltage can be selected.
DV6 0 0 DV5 0 0 DV4 0 0 DV3 1 1 DV2 0 0 DV1 0 0 DV0 0 1 Output Voltage 8 (Smaller)
1 1
1 1
1 1
0 1
1 0
1 0
1 0 120 (Larger)
The output voltage at VBA is specified by equation (1).
M + Offset VBA = 1 + x VREF 381
where M: DV register value Offset: CV1~CV4 setting VREF: internal temperature compensation output voltage VBA ranges from 1.5V to 2V at 25 C
(1)
The LCD driver voltage V0 is determined by the VBA level and the RM register value in equation (2).
V 0 = VBA x N
where N : RM register setting
(2)
The relationship between V0 and DV setting values (when Vref = 1.5V) is shown below:
V0 vs DV (Vref=1.5V)
20 19 18 17 16 15 14 13 V0 12 11 10 9 8 7 6 5 4 0 16 32 48 64 DV 80 96 112
RM=9.5 RM=8.9 RM=8.5 RM=8.0 RM=7.5 RM=6.0 RM=4.5 RM=3
90 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver In order to prevent a transient voltage from being generated when an electronic volume code is set, the circuit is designed in such a way that the set value is not reflected immediately as a level but only after the upper bits (DV6-DV4) of the electronic code have been set. The set value becomes valid when the lower bits (DV3-DV0) of the electronic control volume code have also been set.
8.2.19 Resistance Ratio of CR Oscillator
D7 1 D6 1 D5 0 D4 1 D3 * D2 D1 D0 CSB RS RDB 0 1 1 WRB 0 RE2 RE1 RE0 1 0 0 RF2 RF1 RF0
Note: During a reset: {RF2, RF1, RF0} = 0H, read address: DH The asterisk "*" mark means "Don't care" The RF registers can control the resistance ratio of the CR oscillator. Therefore the frame frequency can change the RF register setting. When changing the RF register value, the LCD display quality should be checked.
RF2 0 0 0 0 1 1 1 1 RF1 0 0 1 1 0 0 1 1 RF0 0 1 0 1 0 1 0 1 Operation Initial Resistance Ratio 0.7 times the Initial Resistance Ratio 0.85 times the Initial Resistance Ratio 1.15 times the Initial Resistance Ratio 1.3 times the Initial Resistance Ratio Code Prohibited Code Prohibited Code Prohibited
8.2.20 Extended Power Control
D7 1 D6 1 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0 BF1 BF0 HPM DIS
Note: During a reset: {HPM, DIS} = 0H, {BF1, BF0}= 0H; read address: EH DIS The DIS register can control capacitors discharge that are connected between the power supply V0-V4 for LCD driver voltage and VSS. When using this register, refer to 7-30 (Discharge circuit). DIS = "0": Discharge OFF DIS = "1": Discharge start HPM The HPM register is the power control for the liquid crystal driver power supply circuit. HPM= "H": High power mode HPM= "L": Normal mode
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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130COM/128SEG 65K Color STN LCD Driver BF BF1~BF0: Select the booster operating frequency. When the boosting frequency is high, the driving ability of the booster becomes high, but the current consumption is increased. When adjusting the boosting frequency, consider the external capacitors and the current consumption.
BF1 0 0 1 1 BF0 0 1 0 1 Booster Operating Clock Frequency 1.5kHz x 8 1.5kHz x 4 1.5kHz x 2 1.5kHz
8.2.21 Internal Register Read Address
D7 1 D6 1 D5 0 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 1 0 1 RE1 0 RE0 0 RA3 RA2 RA1 RA0
Note: During a reset: {RA3, RA2, RA1, RA0} = BH The RA register is set to specify the address for the register read operation. The EM65571 has many registers, including a register bank. There are 4 steps necessary to read a specific register. 1. Write 04H to the RE register to access the RA register. 2. Write a specific register address to the RA register. 3. Write a specific register bank to the RE register. 4. Read the specific contents.
8.2.22 Internal Register Data Read
D7 D6 D5 D4 * * * * D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 0 1 0/1 RE1 0/1 RE0 0/1 Internal Register Read Data
Note: The asterisk "*" mark means "Don't care" This command is used to read data from an internal register. Before executing the command, you need to set the address and RE flag to read data from the internal register.
8.2.23 Windows End X Address
D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 1 0 1 RE1 0 RE0 1 EX3 EX2 EX1 EX0
Note: During a reset: {EX3, EX2, EX1, EX0} = 0H, read address: 0H
D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 1 0 1 RE1 0 RE0 1
EX7 EX6 EX5 EX4
Note: During a reset: {EX7, EX6, EX5, EX4} = 0H, read address: 1H) The asterisk "*" mark means "Don't care" Set the EX registers to the X-direction end address for Windows function.
92 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
8.2.24
D7 0 0
Windows End Y Address
D6 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB 1 0 RE2 1 RE1 0 RE0 1 EY3 EY2 EY1 EY0
Note: During a reset: {EY3, EY2, EY1, EY0} = 0H, read address: 2H
D7 0 D6 0 D5 1 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB 1 0 RE2 1 RE1 0 RE0 1
EY7 EY6 EY5 EY4
Note: During a reset: {EY7, EY6, EY5, EY4} = 0H, read address: 3H The asterisk "*" mark means "Don't care" Set the EY registers to the Y-direction end address for Windows function.
8.2.25 Line Reverse Start Address
D7 0 D6 1 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 1 0 1 RE1 0 RE0 1 LS3 LS2 LS1 LS0
Note: During a reset: {LS3, LS2, LS1, LS0} = 0H, read address: 4H
D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB 1 0 RE2 1 RE1 0 RE0 1
LS7 LS6 LS5 LS4
Note: During a reset: {LS7, LS6, LS5, LS4} = 0H, read address: 5H The asterisk "*" mark means "Don't care" Set the LS registers to line reverse start address, then the following two conditions must be kept. 1. 00H LS 7FH 2. LS LE LE: Line reverse end address
8.2.26 Line Reverse End Address
D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 1 0 1 RE1 0 RE0 1 LE3 LE2 LE1 LE0
(During a reset: {LE3, LE2, LE1, LE0} = 0H, read address: 6H)
D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB 1 0 RE2 1 RE1 0 RE0 1
LE7 LE6 LE5 LE4
(During a reset: {LE7, LE6, LE5, LE4} = 0H, read address: 7H) Set the LE registers to line reverse end address, then the following two conditions must be kept. 1. 00H LS 7FH 2. LS LE LS: Line reverse start address
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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130COM/128SEG 65K Color STN LCD Driver
8.2.27
D7 1 0
Line Reverse Control
D6 D5 0 D4 0 D3 * D2 BST D1 BT D0 LREV CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 1 0 1
Note: During a reset: {BST, BT, LREV} = 0H, read address: 8H The asterisk "*" mark means "Don't care" BST The BST register controls the Fast Burst RAM write function BST = "0": Burst RAM write function OFF BST = "1": Burst RAM write function ON LREV The LREV registers control line reverse display function. LREV = "0": Normal display (Not reverse). LREV = "1": Line reverse display enable. The area specified by the Line Reverse Start/End Register reverse display. The reverse type is selectable by BT register. When using the Line Reverse Display function, the LS and LE registers must keep the following relation: LS LE BT The BT register controls the line reverse type. This is an option for the line reverse display function. This BTs setting is only available when LREV="1" BT = "0": Reverse display BT = "1": Reverse display for each 32 frame.
Display change each 32 frame
Blink example (LREV = "1", BT = "1")
The LREV and BT setting don't influence the special segment outputs. The display area selected by COMA and COMB common outputs are also not influenced.
94 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
ELAN LCD DRIVER Low Power and Low Voltage
Display change each 32 frame
ELAN
Line reverse start address
LCD DRIVER Low Power and Low Voltage
Line reverse end address
Blink example (LREV = "1", BT = "1")
8.2.28 Regulator Multiple Ratio Control Register
The V0 steps set to RM register.
D7 1 D6 0 D5 0 D4 1 D3 * D2 D1 D0 CSB 0 RS RDB WRB RE2 RE1 RE0 1 1 0 0 0 0
RM2 RM1 RM0
Note: During a reset: {RM2, RM1, RM0} = 0H, read address: 9H The asterisk "*"mark means "Don't care" The booster steps set to RM register.
RM2 0 0 0 0 1 1 1 1 RM1 0 0 1 1 0 0 1 1 RM0 0 1 0 1 0 1 0 1 Regulator Multiple Ratio Control 3.0 times the Voltage Output 4.5 times the Voltage Output 6.0 times the Voltage Output 7.5 times the Voltage Output 8.0 times the Voltage Output 8.5 times the Voltage Output 8.9 times the Voltage Output 9.5 times the Voltage Output
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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130COM/128SEG 65K Color STN LCD Driver
8.2.29 EEPROM Mode Select Register
D7 D6 D5 D4 D3 D2 1 0 1 0 M1 M0 D1 VPP_EXT D0 OSC CSB RS 0 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
Note: During a reset: {M1, M0, VPP_EXT, OSC} = CH, read address: AH The (M1, M0) register control EEPROM mode
(M1, M0) 00 01 10 11 EEPROM Operating Mode Read Program Erase Reserve
The VPP_EXT register controls the EEPROM power selection. VPP_EXT=0 Program or Erase EEPROM voltage is from an internal power source. VPP_EXT=1 Program or Erase EEPROM voltage is from an external power source. 16~18V is from an external VPP pin. The OSC register controls the oscillator frequency selection. OSC=0 Initial oscillator frequency setting OSC=1 Oscillator frequency + 50%
8.2.30 Vop Calibration Offset Register
D7 1 D6 0 D5 1 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB 1 WRB 0 RE2 RE1 RE0 1 0 1 CV4 CV3 CV2 CV1
Note: During a reset: {CV4, CV3, CV2, CV1} = 0H, read address: BH) The CV4~CV1 register controls the Vop calibration offset voltage selection.
M + Offset VBA = 1 + x VREF 381
where M: DV register setting Offset: CV1~CV4 setting
CV4-CV1 0111 0110 ... 0000 1000 1001 ... 1111 Calibration Offset +7 +6 ... 0 -8 -7 ... -1
96 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
9
Relationship between Setting and Common/Display RAM
The relationship between the COM pin numbers and the addresses in the Y-direction on the display RAM changes according to the SHIFT command, LCD Duty Set command, Display Starting Common Position Set command, and Display Starting Line Set command. When "0" is selected for the display starting line: The relationship between the COM pin and the addresses in the vertical direction of the display RAM (hereafter called MY) changes on a 15-dot basis according to the LCD Duty Set command and the Display Starting Common Position Set command. The common positions change in the forward direction when the SHIFT bit is "0", and change in the reverse direction when the SHIFT bit is "1". When "0" is selected as the value for LA7 to LA0 in the Display Starting Line Set command, the MY number corresponding to the display starting position is "0". The MY numbers are sequentially shifted backward when display occurs. In any case, the relations of COMA = MY160 and COMB = MY161 do not change. When non-zero is selected for the display starting line: The relationship between the COM pins and the addresses in the vertical direction on the display RAM MY changes on a 15-dot basis according to the information in the LCD Duty Set command and Display Starting Common Position Set command. The common positions change in the forward direction when the SHIFT bit is "0", and change in the reverse direction when the SHIFT bit is "1". If non-zero is selected for the values for LA7 to LA0 in the Display Starting Line set command. The MY number corresponding to the display starting position shifts with the set value. The MY number shifts backward when display occurs. If it exceeds 159, it returns to 0, and then shifts sequentially. In any case, the relations of COMA = MY160 and COMB = MY161 do not change. When you want a mirror image in the Y-direction like the following figure, you must set additional commands to complete this operation:
WRITE 0xF0 WRITE 0x8D WRITE 0x22 WRITE 0xF4 WRITE 0x63
//bank 0 //shift=1 ; 65k color ; display on //Y address=2 //bank 4 //SC=0011
* 97
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
10 Absolute Maximum Ratings
10.1 Absolute Maximum Ratings
Item Supply Voltage (1) Supply Voltage (2) Supply Voltage (3) Supply Voltage (4) Supply Voltage (5) Supply Voltage (6) Input Voltage Storage Temperature Symbol VDD VEE VOUT VBA V0 V1, V2, V3, V4 VI Tstg Ta=25 Condition Pin Used VDD VEE VOUT VBA V0 V1, V2, V3, V4 *1 Rating -0.3 ~ + 4.0 -0.3 ~ + 4.0 --0.3 ~ + 20.0 1.5 ~ + 2.0 -0.3 ~ + 18.0 -0.3 ~ V0+ 0.3 -0.3 ~ VDD+ 0.3 -45 ~ +125 Unit V V V V V V V
10.2 Recommended Operating Conditions
Item Supply Voltage Symbol VDD1 VDD2 VEE Operating Voltage V0 VOUT VBA VREF Operating Temperature Topr Pin VDD VDD VEE V0 VOUT VBA VREF -30 1.5 1.5 85 Min. 2.2 2.4 2.4 5 Typ. Max. 3.3 3.3 3.3 18 20 2.0 Unit V V V V V V V Note *1 *2 *3 *4 *5
Power supply for logic circuit. Power supply for analog circuit. Power supply for the internal boosting circuit. If applied voltage is the same as VDD, connect to VDD. Voltage V0>V1>V2>V3>V4>VSS must always be maintained. Voltage VOUT > V0 must always be maintained.
98 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
11 DC Characteristics
VSS=0V, VDD = 2.2 ~3.3V, Ta = -30 ~85C
Item High level input voltage Low level input voltage High level output current Low level output current High level output current Low level output current Input leakage current Output leakage current LCD driver output resistance Standby current through VDD pin Oscillator frequency (variable gradation mode, 65K or 4096 or 256 color mode) Oscillator frequency (48 gradation mode) Oscillator frequency (16 gradation mode) Oscillator frequency (8 gradation mode) Symbol VIH VIL IOH1 IOL1 IOH2 IOL2 ILI1 ILO RON ISTB VOH = VDD-0.4V VOL= 0.4V VOH = VDD-0.4V VOL= 0.4V VI = VSS or VDD VI = VSS or VDD |Von| = 0.5V V0=10V V0=6V Condition Min. 0.8VDD 0 -2.7 2.7 -0.8 0.8 -2 -2 1.0 1.2 Typ. 0.9VDD 0.1VDD -3.2 3.2 -1.0 1.0 0 0 1.3 1.7 5 Max. VDD 0.2VDD -3.5 3.5 -1.2 1.2 2 2 1.6 2.2 15 Unit V V mA mA mA mA A A K A Pin used 1 1 2 2 3 3 4 5 6 7
CK=0, CSB=VDD, Ta=25 , VDD=3V
VDD=3V , Ta=25 , Fosc1 Rf setting = (Rf2, Rf1, Rf0) = (000) VDD=3V, Ta=25 , Fosc2 Rf setting = (Rf2, Rf1, Rf0) = (000) VDD=3V, Ta=25 , Fosc3 Rf setting = (Rf2, Rf1, Rf0) = (000) VDD=3V , Ta=25 , Fosc4 Rf setting = (Rf2, Rf1, Rf0) = (000)
854
1005
1155
kHz
8
602
720
827
kHz
9
296
360
413
kHz
10
148
180
211
kHz
11
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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130COM/128SEG 65K Color STN LCD Driver
Pin used 12 13 14 15 16 17 18 19 20 21 1.01xV0 V
Item
Symbol VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 IDD1
Condition Seven times boosting RL = 500K (VOUT-VSS) Six times boosting RL = 500K (VOUT-VSS) Five times boosting RL = 500K (VOUT-VSS) Four times boosting RL = 500K (VOUT-VSS) Three times boosting RL = 500K (VOUT-VSS) Two times boosting RL = 500K (VOUT-VSS) VDD = 3V, 6 times boosting, All ON pattern VDD = 3V, 6 times boosting, Check pattern VDD =2.4V~3.3V
Min.
Typ.
Max.
Unit V V V V V V A A
7xVEEx0.95 7xVEEx0.98 7xVEEx0.99 (VEE<=2.8) (VEE<=2.8) (VEE<=2.8)
6xVEEx0.95 6xVEEx0.98 6xVEEx0.99 5xVEEx0.95 5xVEEx0.98 5xVEEx0.99 4xVEEx0.95 4xVEE x0.98 4xVEEx0.99 3xVEEx0.95 3xVEEx0.98 3xVEEx0.99 2xVEEx0.95 2xVEEx0.98 2xVEEx0.99 600 800 1.5 1.5 0.99xV0 V0 2.0
Booster output Voltage on VOUT pin
Current consumption IDD2 VBA output voltage VREF output voltage V0 output voltage VBA
V
VREF VDD = 2.4 ~ 3.3V V0 VDD = 2.4 ~ 3.3V
Relationship between the oscillating frequency (fosc) and external clock frequency (fCK) to the LCD frame frequency (fFLM) in each display mode
Original Oscillating Clock Ratio of Display Duty Cycle (1/D) Display Mode 1/130 to 1/98 Variable gradation When using a built-in oscillating circuit (fosc) Simple gradation (65K color) Simple gradation (4096 color) Simple gradation (256 color) Variable gradation When using an external clock from the CK pin. (fCK) Simple gradation (65K color) Simple gradation (4096 color) Simple gradation (256 color) 1/82 to 1/50 1/34 to 1/26 1/18 to 1/10 fosc / (2x47xD) fosc / (4x47xD) fosc / (8x47xD) fosc / (16x47xD) fosc / (2x31xD) fosc / (4x31xD) fosc / (8x31xD) fosc / (16x31xD) fosc / (2x15xD) fosc / (4x15xD) fosc / (8x15xD) fosc / (16x15xD) fosc / (2x7xD) fosc / (4x7xD) fosc / (8x7xD) fosc / (16x7xD)
fCK / (2x47xD) fCK / (4x47xD) fCK / (8x47xD) fCK / (16x47xD) fCK / (2x31xD) fCK / (4x31xD) fCK / (8x31xD) fCK / (16x31xD) fCK / (2x15xD) fCK / (4x15xD) fCK / (8x15xD) fCK / (16x15xD) fCK / (2x7xD) fCK / (4x7xD) fCK /(8x7xD) fCK / (16x7xD)
100 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
D0-D15, CSB, RS, M/S, M86, RDB, WRB, CK, CKS, P/S, RESB, TEST pins D0~D15 pins CLK pins CSB, RS, M/S, M86, RDB, WRB, CK, CKS, P/S, RESB, TEST pins Applied when D0~D15 are in the state of high impedance. SEGA0~SEGA127, SEGB0~SEGB127, SEGC0~SEGC127. DSEGA0~DSEGA1, DSEGB0~DSEGB0 , DSEGC0~DSEGC1, COM0~COM79, COMA, COMB pins Resistance when applied with 0.5V between each output pin and each power supply (V0, V1, V2, V3, V4), and when applied with 1/13 bias. VDD pin. VDD pin current without load when the original oscillating clock stopped and at non-select (CSB=VDD) Oscillating frequency. When using a built-in oscillating circuit (variable gradation display mode 65K, 4096 or 256 color mode) Oscillating frequency. When a built-in oscillating circuit is used (48 gradation fixed display mode) Oscillating frequency. When a built-in oscillating circuit is used (16 gradation fixed display mode) Oscillating frequency. When a built-in oscillating circuit is used (8 gradation fixed display mode) VOUT pin. When the built-in oscillating circuit, built-in power supply, and boosting 7 times are used, this pin is applied. VEE 2.8 V. The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/13, 1/128 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11" VOUT pin. When the built-in oscillating circuit, built-in power supply, and boosting 6 times are used, this pin is applied. VEE = 2.4 ~ 3.3. The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/13, 1/128 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11" VOUT pin. When the built-in oscillating circuit, built-in power supply, and boosting 5 times are used, this pin is applied. VEE=2.4~3.3 V. The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/13, 1/128 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11" VOUT pin. When the built-in oscillating circuit, built-in power supply, and boosting 4 times are used, this pin is applied. VEE=2.4~3.3 V. The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/13, 1/128 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11" VOUT pin. When the built-in oscillating circuit, built-in power supply is used, and boosting 3 times are used, this pin is applied. VEE=2.4~3.3 V. The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/13, 1/128 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11" VOUT pin. When the built-in oscillating circuit, built-in power supply, and boosting 2 times are used, this pin is applied. VEE=2.4~3.3 V. The electronic control is preset (The code is
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 101
EM65571
130COM/128SEG 65K Color STN LCD Driver ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/13, 1/128 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11" VDD, VEE pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from the MPU, this pin is applied. Boosting 6 times is used when the electronic control is preset. (The code is ("1 1 1 1 1 1 1"). Display ALL ON pattern {Rf2, Rf1, Rf0 = ("0 0 0 ") } (on monochrome display mode) and LCD driver pin with no load. Measuring conditions: VDD=VEE , VBA=VREF, C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" , NLIN="0", (BF1, BF0) = (1,1), 1/128 duty, 1/13 bias, BF="11" VDD, VEE pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from the MPU, this pin is applied. Boosting 6 times is used when the electronic control is preset. (The code is ("1 1 1 1 1 1 1"). Display a checkered pattern, {Rf2, Rf1, Rf0 = ("0 0 0 ") } (on monochrome display mode) and LCD driver pin with no load. Measuring conditions: VDD=VEE, C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" , NLIN="0" ,(BF1,BF0)=(1,1) ,1/128 duty , 1/13 bias, BF="11" VBA pin. Measuring conditions: N times boosting (N=2~7), electronic control= "1 1 1 1 1 1 1", Displays a checkered pattern , DCON=AMPON="1" , NLIN="0" , 1/128 duty , VDD=VEE, VBA=VREF , C1=C2=1.0F, C3=0.1F , no load VREF pin. Measuring conditions: VDD = 3 volt, N times boosting (N=2 ~ 7), electronic control = "1 1 1 1 1 1 1", DCON=AMPON="1", NLIN="0", 1/128 duty. Note: The capacitor C1 is used for booster related pin. CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, CAP1- , CAP4+ , CAP2- , CAP5+, CAP1-, CAP6+, CAP1- and VOUT, VSS The capacitor C2 is used for bias related pin. V0, V1, V2, V3, V4
12 AC Characteristic
12.1 80-family MPU Write Timing
tAS8 tAH8
CSB RS
tW RLW 8 W RB tDS8 tW RHW 8 tDH8
D0-D15
tCYCW R8
102 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
VSS = 0V, VDD = 2.7~3.3V, Ta = -30 ~ +85C
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 0 0 200 30 135 60 5 Typ. Max. Unit Pin Used ns ns ns ns ns ns ns CSB RS WRB (R/WB)
D0~D15
VSS = 0V, VDD = 2.4~2.7V, Ta = -30 ~ +85C
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 0 0 250 50 160 80 10 Typ. Max. Unit Pin Used ns ns ns ns ns ns ns CSB RS WRB (R/WB)
D0~D15
VSS = 0V, VDD = 2.2~2.4V, Ta = -30 ~ +85C
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 0 0 500 100 350 100 20 Typ. Max. Unit Pin Used ns ns ns ns ns ns ns CSB RS WRB (R/WB)
D0~D15
Note: All the timings must be specified relative to 20% and 80% of the VDD voltage.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 103
EM65571
130COM/128SEG 65K Color STN LCD Driver
12.2 80-Family MPU Read Timing
tAS8 CSB RS tAH8
RDB
tRDLW 8 tRDHW 8 tRDH8
tRDD8 D0-D15
tCYCRD8
VSS = 0V, VDD = 2.7~3.3V, Ta = -30 ~ +85C
Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8 CL = 80 pF 10 Condition Min. 0 0 380 200 170 210 Typ. Max. Unit Pin Used ns ns ns ns ns ns ns D0~D15 RDB (E) CSB RS
VSS = 0V, VDD = 2.4~2.7V, Ta = -30 ~ +85C
Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8 CL = 80 pF 10 Condition Min. 0 0 540 290 230 300 Typ. Max. Unit Pin Used ns ns ns ns ns ns ns D0~D15 RDB(E) CSB RS
104 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver VSS = 0V, VDD = 2.2~2.4V, Ta = -30 ~ +85C
Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8 CL = 80 pF 10 Condition Min. 0 0 840 440 380 450 Typ. Max. Unit Pin Used ns ns ns ns ns ns ns D0~D15 RDB(E) CSB RS
Note: All the timings must be specified relative to 20% and 80% of the VDD voltage.
12.3 68-Family MPU Write Timing
tAS6 CSB RS tAH6
R/W B (W RB)
E (RDB)
tEHW 6
tELW 6
tDS6
tDH6
D0-D15
tCYCW R6
VSS = 0V, VDD = 2.7 ~3.3V, Ta = -30 ~ +85C
Item Address hold time Address setup time Symbol tAH6 tAS6 Condition Min. 0 0 200 30 135 60 5 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
System cycle time in write tCYCWR6 Write pulse "L" width Write pulse "H" width Data setup time Data hold time tELW6 tEHW6 tDS6 tDH6
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 105
EM65571
130COM/128SEG 65K Color STN LCD Driver VSS=0V, VDD = 2.4 ~2.7V, Ta = -30 ~ +85C
Item Address hold time Address setup time Symbol tAH6 tAS6 Condition Min. 0 0 250 50 160 80 10 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
System cycle time in write tCYCWR6 Write pulse "L" width Write pulse "H" width Data setup time Data hold time tELW6 tEHW6 tDS6 tDH6
VSS = 0V, VDD = 2.2 ~2.4V, Ta = -30 ~ +85C
Item Address hold time Address setup time Symbol tAH6 tAS6 Condition Min. 0 0 500 100 350 100 20 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
System cycle time in write tCYCWR6 Write pulse "L" width Write pulse "H" width Data setup time Data hold time tELW6 tEHW6 tDS6 tDH6
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
12.4 68-Family MPU Read Timing
tAS6 CSB RS tAH6
R/W B (W RB)
E (RDB)
tEHW 6
tELW 6
tRDD6
tRDH6
D0-D15
tCYCRD6
106 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver VSS = 0V, VDD = 2.7~3.3V, Ta = -30 ~ +85C
Item Address hold time Address setup time System cycle time in read Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 CL=50pF Condition Min. 0 0 380 200 170 210 10 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
VSS = 0V, VDD = 2.4~2.7V, Ta = -30 ~ +85C
Item Address hold time Address setup time System cycle time in read Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 CL=50pF Condition Min. 0 0 540 290 230 300 10 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
14.4.3VSS = 0V, VDD = 2.2~2.4V, Ta = -30 ~ +85C
Item Address hold time Address setup time System cycle time in read Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 CL=50pF Condition Min. 0 0 1000 450 500 650 10 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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130COM/128SEG 65K Color STN LCD Driver
12.5 Serial Interface Timing Diagram
tCSS CSB tCSH
RS tASS tSLW SCL tDSS
tAHS
tSHW
tDHS
D0-D15
tCYCS
VSS = 0V, VDD = 2.7~3.3V, Ta = -30 ~ +85C
Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 200 80 80 40 40 80 80 40 40 Typ. Max. Unit Pin Used ns ns ns ns ns ns ns ns ns RS SCL
SDA
CSB
VSS = 0V, VDD = 2.4~2.7V, Ta = -30 ~ +85C
Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 200 80 80 50 50 80 80 50 60 Typ. Max. Unit Pin Used ns ns ns ns ns ns ns ns ns RS SCL
SDA
CSB
108 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
130COM/128SEG 65K Color STN LCD Driver
VSS = 0V, VDD = 2.2~2.4V, Ta = -30 ~ +85C
Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 230 100 100 80 80 100 100 80 100 Typ. Max. Unit Pin Used ns ns ns ns ns ns ns ns ns RS SCL
SDA
CSB
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
12.6 Clock Input Timing
tCKLW CK tCKHW
VSS = 0V, VDD = 2.4~3.3V, Ta = -30 ~ +85C
Item CK pulse "H" width (1) CK pulse "L" width (1) CK pulse "H" width (2) CK pulse "L" width (2) CK pulse "H" width (3) CK pulse "L" width (3) Symbol tCKHW1 tCKLW1 tTCKHW2 tCKLW2 tCKHW3 tCKLW3 Condition Min. 1.2 1.2 5.4 5.4 3.8 3.8 Typ. Max. 1.4 1.4 6.5 6.5 4.5 4.5 Unit s s s s s s Pin Used CK 1 CK 2 CK 3
VSS = 0V, VDD = 2.2~2.4V, Ta = -30 ~ +85C
Item CK pulse "H" width (1) CK pulse "L" width (1) CK pulse "H" width (2) CK pulse "L" width (2) CK pulse "H" width (3) CK pulse "L" width (3)
1
Symbol tCKHW1 tCKLW1 tCKHW2 tCKLW2 tCKHW3 tCKLW3
Condition Note1 Note1 Note2 Note2 Note3 Note3
Min. 1.2 1.2 5.4 5.4 3.8 3.8
Typ.
Max. 1.4 1.4 6.5 6.5 4.5 4.5
Unit s s s s s s
Pin used CK
1
CK 2
CK 3
Note: Applied when the gradation display mode, 65K="0", PWM="0" 2 Applied when the simple gradation mode, 65K="0", PWM="1" 3 Applied when the monochrome mode, 65K="1"
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
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130COM/128SEG 65K Color STN LCD Driver
12.7 Reset Timing
RESB tRW tR
Internal State
Reset Mode
Normal Display
VSS = 0V, VDD = 2.4~3.3V, Ta = -30 ~ +85 C
Item Reset time Reset pulse "L" width Symbol tR tRW 10 Condition Min. Typ. Max. 1 Unit s s RESB Pin Used
VSS = 0V, VDD = 2.2~2.4V, Ta = -30 ~ +85C
Item Reset time Reset pulse "L" width Symbol tR tRW 10 Condition Min. Typ. Max. 1.5 Unit s s RESB Pin Used
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
13 Application Circuit
13.1 Connections of the 80-Family MPU
VCC A0 A1 to A7 80-family MCU Decoder /IORQ D0 to D15 /RD /WR /RES GND CSB RS
VDD
D0 to D15 RDB WRB RESB VSS
110 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
EM65571
EM65571
130COM/128SEG 65K Color STN LCD Driver
13.2 Connections of the 68-Family MPU
VCC A0 A1 to A15 68-family MCU Decoder VMA D0 to D15 E R/W /RES GND D0 to D15 RDB(E) WRB(R/W) RESB VSS CSB EM65571 RS VDD
13.3 Connection of the MPU with Serial Interface
VCC A0 A1 to A7 MCU RS CSB EM65571 VSS VDD
Decoder
PORT1 PORT2 /RES GND
SDA SCL RESB
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)
* 111
EM65571
130COM/128SEG 65K Color STN LCD Driver
14 Tray Information
Tray Outline Dimension Unit: mm
Symbol L1 L2 L3 T Sx Sy S X Y Dimension 50.60 45.40 45.80 4.00 14.40 5.07 15.27 20.80 1.88 Symbol Z Px Py Nx Ny N P1 P2 Dimension 0.66 21.80 2.38 2 18 36 1.76 1.60
112 *
Product Specification (V1.0) 08.04.2005
(This specification is subject to change without further notice)

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